JPS6214954B2 - - Google Patents

Info

Publication number
JPS6214954B2
JPS6214954B2 JP55012643A JP1264380A JPS6214954B2 JP S6214954 B2 JPS6214954 B2 JP S6214954B2 JP 55012643 A JP55012643 A JP 55012643A JP 1264380 A JP1264380 A JP 1264380A JP S6214954 B2 JPS6214954 B2 JP S6214954B2
Authority
JP
Japan
Prior art keywords
electrodes
power generation
electrode
semiconductor layer
amorphous silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55012643A
Other languages
Japanese (ja)
Other versions
JPS55124274A (en
Inventor
Yukinori Kuwano
Terutoyo Imai
Masakazu Umetani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP1264380A priority Critical patent/JPS55124274A/en
Publication of JPS55124274A publication Critical patent/JPS55124274A/en
Publication of JPS6214954B2 publication Critical patent/JPS6214954B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F19/00—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules
    • H10F19/30—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising thin-film photovoltaic cells
    • H10F19/31—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising thin-film photovoltaic cells having multiple laterally adjacent thin-film photovoltaic cells deposited on the same substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Landscapes

  • Photovoltaic Devices (AREA)

Description

【発明の詳細な説明】 本発明は非晶質シリコンの如き非晶質半導体を
用いた太陽電池に関し、特にその特性の向上を図
つたものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solar cell using an amorphous semiconductor such as amorphous silicon, and is particularly aimed at improving the characteristics thereof.

図は本発明実施例を示し、1はガラス等の透光
性絶縁基板、2a,2b,2cは該基板上に複数
個所定方向に配列被着された第1電極、3a,3
b,3cは夫々第1電極2a,2b,2c上に被
着された非晶質シリコン層、4a,4b,4cは
夫々非晶質シリコン層3a,3b,3c上に被着
された第2電極、5は上記第1電極、非晶質シリ
コン層、第2電極の積層体を該第2電極側から密
着包囲する絶縁膜である。
The figure shows an embodiment of the present invention, in which 1 is a transparent insulating substrate such as glass, 2a, 2b, 2c are first electrodes arranged in a predetermined direction on the substrate, 3a, 3
b, 3c are amorphous silicon layers deposited on the first electrodes 2a, 2b, 2c, respectively; 4a, 4b, 4c are the second amorphous silicon layers deposited on the amorphous silicon layers 3a, 3b, 3c, respectively. The electrode 5 is an insulating film that tightly surrounds the laminate of the first electrode, the amorphous silicon layer, and the second electrode from the second electrode side.

上記第1電極の各々と、それに隣り合う第2電
極の各々とは、各隣接対向間において、互いに上
記配列方向に延びる延長部10,11を有し、該
延長部にて重畳され接続されている。より詳しく
は、上記絶縁基板1上に配列された複数の第1電
極2a,2b,2cの隣接対向間は、各領域にお
いて第1電極2a,2b,2c、非晶質シリコン
層3a,3b,3c及び第2電極4a,4b,4
cの積層体からなる発電区域12a,12b,1
2cの内左隣りの非晶質シリコン層3a,3bが
延在することにより、当該隣接対向間を埋めてい
る。そして、非晶質シリコン層3a,3bが隣接
対向間を埋めた左隣りの発電区域12a,12b
の第2電極4a,4bの延長部11,11は、上
記非晶質シリコン層3a,3bの延長部分を越え
て絶縁基板1と接することなく右隣りの発電区域
12b,12cの第1電極2b,2cの延長部1
0,10に立下ることにより電気的接続が施され
ている。
Each of the first electrodes and each of the second electrodes adjacent thereto have extension portions 10 and 11 extending in the arrangement direction between adjacent opposing sides, and are overlapped and connected at the extension portions. There is. More specifically, between the plurality of first electrodes 2a, 2b, 2c arranged on the insulating substrate 1, the first electrodes 2a, 2b, 2c, amorphous silicon layers 3a, 3b, 3c and second electrodes 4a, 4b, 4
Power generation areas 12a, 12b, 1 made of a laminate of c.
The adjacent amorphous silicon layers 3a and 3b on the left side of the layer 2c extend to fill the space between the adjacent opposing layers. Then, amorphous silicon layers 3a and 3b fill the gap between adjacent power generating areas 12a and 12b on the left.
The extended portions 11, 11 of the second electrodes 4a, 4b do not touch the insulating substrate 1 beyond the extended portions of the amorphous silicon layers 3a, 3b, but extend to the first electrodes 2b of the power generation areas 12b, 12c on the right. , 2c extension 1
Electrical connection is established by falling to 0 and 10.

この様に、左隣りの発電区域12a,12bか
ら右隣りの発電区域12b,12cの第1電極2
b,2c延長部10,10に向つて延びた第2電
極4a,4bの延長部11,11は、非晶質シリ
コン層3a,3bの右側端を越えて断線事故を招
く大きな段差を立下つて一旦絶縁基板1の表面に
降下するのではなく、第1電極2b,2cの膜厚
で上記段差が緩和された第1電極2b,2cの延
長部10,10に直接立下つているので、斯る大
きな段差に起因する断線事故が防止されている。
In this way, the first electrode 2 of the power generation areas 12a, 12b on the left to the power generation areas 12b, 12c on the right
The extensions 11, 11 of the second electrodes 4a, 4b extending toward the extensions 10, 10 of b, 2c extend beyond the right ends of the amorphous silicon layers 3a, 3b, creating a large step that may cause a disconnection accident. Then, instead of falling once onto the surface of the insulating substrate 1, it falls directly onto the extensions 10, 10 of the first electrodes 2b, 2c, where the step difference is alleviated by the film thickness of the first electrodes 2b, 2c. Wire breakage accidents caused by such large steps are prevented.

上記第1電極は透光性を有し、酸化錫、酸化イ
ンジウム、酸化インジウム錫(In2O3+xSnO2、
X≦0.1)などで構成され、上記第2電極はアル
ミニウム、クロムなどで構成されている。
The first electrode has translucency and is made of tin oxide, indium oxide, indium tin oxide (In 2 O 3 +xSnO 2 ,
X≦0.1), and the second electrode is made of aluminum, chromium, or the like.

上記非晶質シリコン層は光照射により発電に寄
与する電子及び又は正孔を発生するもので、具体
的には、上記第1電極側から順次積層されたP型
層、ノンドーブ層及びN型層の3層構造となつて
いる。斯る非晶質シリコン層はシランなどのシリ
コン化合物ガスやP型、N型各不純物ガスを含む
雰囲気中でのグロー放電により順次堆積形成され
る。尚、上記P型層は膜厚40〜1000Å、ドーブ量
0.01〜1%、ノンドープ層は膜厚0.5〜2μm、
N型層は膜厚200〜1000Å、ドーブ量0.1〜3%で
ある。
The amorphous silicon layer generates electrons and/or holes that contribute to power generation when irradiated with light. Specifically, the amorphous silicon layer includes a P-type layer, a non-doped layer, and an N-type layer that are sequentially stacked from the first electrode side. It has a three-layer structure. Such an amorphous silicon layer is sequentially deposited by glow discharge in an atmosphere containing silicon compound gas such as silane and P-type and N-type impurity gases. The above P-type layer has a thickness of 40 to 1000 Å and a dove amount.
0.01~1%, non-doped layer thickness 0.5~2μm,
The N-type layer has a thickness of 200 to 1000 Å and a dope amount of 0.1 to 3%.

上記装置において、基板1及び第1電極を介し
て光が非晶質シリコン層に入ると、主にノンドー
ブ層において自由状態の電子及び又は正孔が発生
し、これらは上記各層の作るPIN接合電界により
引かれて移動した後対向する第1電極や第2電極
に集められ両電極間に電圧が発生する。このと
き、左側の第2電極4aと中央の第1電極2b、
中央の第2電極4bと右側の第1電極2cが夫々
電気的接続された状態にあり、従つて上記各対向
電極間の起電圧は直列的に相加される。
In the above device, when light enters the amorphous silicon layer via the substrate 1 and the first electrode, free state electrons and/or holes are generated mainly in the non-doped layer, and these are caused by the PIN junction electric field created by each layer. After being pulled by and moving, it is collected at the opposing first and second electrodes, and a voltage is generated between the two electrodes. At this time, the second electrode 4a on the left, the first electrode 2b in the center,
The second electrode 4b at the center and the first electrode 2c at the right side are electrically connected, so that the electromotive voltages between the opposing electrodes are added in series.

上記絶縁膜5は酸化シリコンや窒化シリコンな
どで構成されており、シランガスと酸素又は窒素
ガスを含む雰囲気中でのグロー放電により、ある
いはアルゴン及び酸素又は窒素ガス雰囲気で石英
ガラスをスパツタする反応性スパツタにより形成
することができる。斯る絶縁膜は装置の機械的保
護並びに第2電極や非晶質シリコン層を外界から
完全に遮断し、湿気や腐蝕性ガスなどから装置を
護もる。
The insulating film 5 is made of silicon oxide, silicon nitride, etc., and is formed by glow discharge in an atmosphere containing silane gas and oxygen or nitrogen gas, or by reactive sputtering in which quartz glass is sputtered in an argon and oxygen or nitrogen gas atmosphere. It can be formed by Such an insulating film provides mechanical protection for the device, completely shields the second electrode and the amorphous silicon layer from the outside world, and protects the device from moisture, corrosive gases, and the like.

上記実施例装置はPIN接合型であつたがシヨツ
トキ型も実施でき、又実施例装置ではガラス基板
1側から光入射を行なつていたが、絶縁膜5及び
第2電極4a,4b,4cを透光性になすことに
より絶縁膜5側から光入射をなすこともできる。
Although the device in the above embodiment was of the PIN junction type, a shotgun type could also be implemented.Also, in the device of the embodiment, light was incident from the glass substrate 1 side, but the insulating film 5 and the second electrodes 4a, 4b, 4c were By making it transparent, light can also be incident from the insulating film 5 side.

さて、上記太陽電池に光入射を行ない、かつ例
えば左端の第1電極2aと右端の第2電極4cと
の間に負荷を接続すれば太陽電池の光起電圧に基
づく電流が上記負荷に流れるが、このときの光電
変換効率は太陽電池の内部抵抗に依存する。斯る
内部抵抗は主に、対をなす第1電極と第2電極及
びこれら電極間に介在する非晶質シリコン層から
なる構成を一つの発電区域となすと、各発電区域
12a,12b,12c間の直列抵抗により決ま
り該抵抗は小さいほど良いが、本発明実施例太陽
電池にあつては、隣り合う第1、第2電極はその
隣接対向間において、互いに上記配列方向に延び
る延長部10,11にて重畳接続されているの
で、各発電区域間の電気的接続は上記配列方向に
垂直な方向(即ち第1図にて紙面に垂直な方向)
において例えば各発電区域の全幅(第2図L)に
亘つて行なうことができるなど、ほゞ最短距離か
つ十分な長さにて行なうことができ、各区域間の
電流が一部に集中することなく各発電区域間の直
列抵抗を小さくすることができる。
Now, if light is incident on the solar cell and a load is connected, for example, between the first electrode 2a on the left end and the second electrode 4c on the right end, a current based on the photovoltaic voltage of the solar cell will flow to the load. , the photoelectric conversion efficiency at this time depends on the internal resistance of the solar cell. Such internal resistance is mainly caused by each power generation area 12a, 12b, 12c when one power generation area is composed of a pair of first and second electrodes and an amorphous silicon layer interposed between these electrodes. The resistance is determined by the series resistance between them, and the smaller the better, but in the solar cell according to the embodiment of the present invention, the adjacent first and second electrodes have extension portions 10 extending in the arrangement direction, 11, the electrical connection between each power generation area is perpendicular to the above arrangement direction (i.e., the direction perpendicular to the paper in Fig. 1).
For example, it can be carried out over the shortest distance and sufficient length, such as across the entire width of each power generation area (L in Figure 2), and the current between each area can be concentrated in one part. It is possible to reduce the series resistance between each power generation area.

以上の説明より明らかな如く、本発明によれば
非晶質半導体を用いた複数の発電区域からなる太
陽電池において、各発電区域間の直列抵抗を十分
小さくすることができ、大なる光電変換効率を得
ることができる。又、上記各発電区域間の直列抵
抗が小さいので各発電区域の直列段数を容易に増
すことができより高い出力電圧の太陽電池を実現
することができる。更に、第1電極の隣接対向間
において一方の発電区域から他方の発電区域の第
1電極延長部に向つて延びた第2電極延長部は、
非晶質半導体層の側端を越えて該半導体層の膜厚
に相当する大きな段差を立下つて一旦絶縁基板の
表面に降下するのではなく、第1電極の膜厚で上
記段差が緩和された第1電極の延長部に直接立下
つているので、斯る大きな段差に起因する断線事
故を防止するのみならず、第1電極の隣接対向間
における絶縁も確実なものとすることができる。
従つて、斯る隣接対向間の間隔縮小が図れ、受光
面積における発電区域が占める割合を増大させる
ことができる。
As is clear from the above explanation, according to the present invention, in a solar cell using an amorphous semiconductor and consisting of a plurality of power generation regions, the series resistance between each power generation region can be sufficiently reduced, and the photoelectric conversion efficiency can be increased. can be obtained. Further, since the series resistance between the power generation sections is small, the number of series stages of each power generation section can be easily increased, and a solar cell with a higher output voltage can be realized. Furthermore, a second electrode extension extending from one power generation area toward the first electrode extension of the other power generation area between adjacent opposing first electrodes,
Rather than going beyond the side edge of the amorphous semiconductor layer and falling down a large step corresponding to the thickness of the semiconductor layer and once dropping to the surface of the insulating substrate, the step is alleviated by the thickness of the first electrode. Since the first electrodes fall directly on the extended portions of the first electrodes, it is possible not only to prevent disconnection accidents caused by such large steps, but also to ensure insulation between adjacent first electrodes.
Therefore, it is possible to reduce the distance between the adjacent facing units, and increase the proportion of the light-receiving area occupied by the power generation area.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は夫々本発明実施例を示す断
面図及び斜視図である。 1……基板、3a,3b,3c……非晶質シリ
コン層、5……絶縁膜。
1 and 2 are a sectional view and a perspective view, respectively, showing an embodiment of the present invention. 1...Substrate, 3a, 3b, 3c...Amorphous silicon layer, 5...Insulating film.

Claims (1)

【特許請求の範囲】[Claims] 1 絶縁基板上に配列された複数の第1電極、該
第1電極の各々に対応し、夫々の上に順次被着さ
れた非晶質半導体層及び第2電極を備え、隣り合
う第1、第2電極はその隣接対向間において互い
に上記配列方向に延びて重畳接続されている太陽
電池であつて、上記絶縁基板上に配列された複数
の第1電極の隣接対向間は、一方の発電区域を構
成する非晶質半導体層が延在して当該隣接対向間
を埋めると共に、一方の発電区域の第2電極の延
長部は上記非晶質半導体層の延在部分を越えて絶
縁基板と接することなく他方の発電区域の第1電
極延長部に立下ることを特徴とした太陽電池。
1 A plurality of first electrodes arranged on an insulating substrate, an amorphous semiconductor layer and a second electrode corresponding to each of the first electrodes and sequentially deposited on each of the first electrodes; The second electrodes are connected to each other in an overlapping manner so as to extend in the arrangement direction between adjacent second electrodes, and the plurality of first electrodes arranged on the insulating substrate are arranged in one power generation area. The amorphous semiconductor layer constituting the amorphous semiconductor layer extends to fill the gap between the adjacent opposing sides, and the extended portion of the second electrode of one power generation area contacts the insulating substrate beyond the extended portion of the amorphous semiconductor layer. A solar cell characterized in that the first electrode extension part of the other power generation area falls without falling.
JP1264380A 1980-02-04 1980-02-04 Solar battery Granted JPS55124274A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1264380A JPS55124274A (en) 1980-02-04 1980-02-04 Solar battery

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1264380A JPS55124274A (en) 1980-02-04 1980-02-04 Solar battery

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP3130579A Division JPS55123177A (en) 1979-02-09 1979-03-16 Solar cell

Publications (2)

Publication Number Publication Date
JPS55124274A JPS55124274A (en) 1980-09-25
JPS6214954B2 true JPS6214954B2 (en) 1987-04-04

Family

ID=11811037

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1264380A Granted JPS55124274A (en) 1980-02-04 1980-02-04 Solar battery

Country Status (1)

Country Link
JP (1) JPS55124274A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58134482A (en) * 1982-02-05 1983-08-10 Agency Of Ind Science & Technol Photovoltaic device
JPS6122370U (en) * 1984-07-12 1986-02-08 富士電機株式会社 photovoltaic element
EP0213910B1 (en) 1985-08-24 1994-03-02 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device free from the current leakage through a semi-conductor layer
KR20100076083A (en) 2008-12-17 2010-07-06 서울반도체 주식회사 Light emitting diode having plurality of light emitting cells and method of fabricating the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3483038A (en) * 1967-01-05 1969-12-09 Rca Corp Integrated array of thin-film photovoltaic cells and method of making same
US3571915A (en) * 1967-02-17 1971-03-23 Clevite Corp Method of making an integrated solar cell array
JPS5537109B2 (en) * 1972-05-26 1980-09-25
JPS584487B2 (en) * 1974-11-20 1983-01-26 松下電器産業株式会社 Hiyojisouchi
US4064521A (en) * 1975-07-28 1977-12-20 Rca Corporation Semiconductor device having a body of amorphous silicon
US4042418A (en) * 1976-08-02 1977-08-16 Westinghouse Electric Corporation Photovoltaic device and method of making same
DE2827049A1 (en) * 1978-06-20 1980-01-10 Siemens Ag SOLAR CELL BATTERY AND METHOD FOR THEIR PRODUCTION

Also Published As

Publication number Publication date
JPS55124274A (en) 1980-09-25

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