JPS62152157A - Thin film transistor array - Google Patents

Abstract

PURPOSE:To reduce generation of failures in the FET array and reduce the cost through improvement in the yield of manufacture by providing two kinds of thin films to the region where a drain electrode in a broad sense connected electrically to the drain electrode overlaps with the gate wirings. CONSTITUTION:A gate electrode and a first conductive layer which will become the gate wiring 2 are selectively formed on an insulating substrate 1 and a first insulating layer 3 is then deposited thereon. Moreover, non-single crystal silicon compound is deposited, as the semiconductor layer 4, on the substrate 1 including the first conductive layer through the layer 3. This compound 6 is provided as a second conductive layer, and the drain electrode 8 and source electrode 9 are arranged so that they do not overlap with the first conductive layer on the substrate 1. Two kinds of thin films are formed and a number of failures in the FET array is reduced in the region where a transparent conductive film 7 is included in the second conductive layer constituting the electrode 8 or the electrode 8 to which the film 7 is connected overlaps with the gate electrode as the first conductive layer.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to thin film transistor arrays, in which thin film transistors (hereinafter abbreviated as TPT) using non-single crystal silicon compound semiconductor films such as amorphous silicon are arranged in a matrix or the like. The present invention relates to semiconductor devices.

Conventional technology FIG.
This is a schematic cross-sectional view of the process along the line -A/, and FIG. 4(b) shows a circuit corresponding to FIG. 4(a).

First, as shown in FIG. 6(a), a first metal layer 2, which will become a gate electrode and a gate wiring, is selectively formed on an insulating substrate 1. Next, a first insulating layer 3, a non-single crystal silicon compound semiconductor layer 4 as a semiconductor layer, and a second insulating layer 6 are deposited in this order. Next, as shown in FIG. 4(-) and FIG. 6(b), a second insulating layer 5' is selectively formed so as to remain only in the area that will become the channel after the TFT is completed, and a non-single crystal silicon compound layer 5' is formed. After exposing the semiconductor 114, a non-single-crystal silicon compound layer 6 containing impurities (such as P) is deposited, and a sixth layer is formed.
As shown in Figure (C), the non-single-crystal silicon compound layer 6 containing impurities and the non-single-crystal silicon compound semiconductor layer 4 are sequentially and selectively removed, and the remaining portion of the second insulating layer 5' is removed. An island-shaped non-single crystal silicon compound semiconductor layer 4' containing
Then, a non-single crystal silicon compound layer 6' is formed.

Next, as shown in FIG. 4 (→), a transparent conductive film 7 is selectively formed without overlapping the gate wiring. Then, as shown in FIG. First, a pair of drain electrodes 8 (partially overlapping the transparent conductive film 7), a source electrode, and a source wiring 9 are selectively formed to avoid an offset gate structure.

In addition, a second metal layer is selectively formed so as to overlap the previous gate wiring of the matrix array and the transparent conductive film so as to be connected to the drain electrode (Fig. 4). ).

Finally, using both the drain and source electrodes 8 and 9 as a mask, 6% of the non-single crystal silicon compound layer containing impurities on the second insulating layer 6' is removed.
T is completed.

Problems to be Solved by the Invention Conventionally, the drain electrode 8 including the transparent conductive film 7 for display output and the second metal layer 10 which is one electrode constituting Cadd in FIG. Only one type of gate insulating layer 3 was left in the portion where the drain electrode 8o (hereinafter referred to as the drain electrode 8o in a broad sense) overlaps with the gate wiring. Generally, the first insulating layer 3 on the edge stepped portion X of the gate wiring 2, which is the first metal layer, has weaker chemical resistance than that deposited on a flat portion. For example, the first
The insulating layer 3 is made of SiN produced by plasma CVD method.
x, Consider the case where the semi-quartet layer 4 is amorphous silicon. As in the conventional method, when etching the part constituting the Cadd in FIG. However, only the edge step part X was etched abnormally rapidly, and the first
The edges of the metal layer 20 are exposed, and therefore, when the second metal layer 1o is selectively formed as shown in FIG.
and the gate wiring 2 (first metal layer) are short-circuited,
It becomes defective.

In addition, when attempting to electrically insulate two layers of gold or gold using one type of insulating film, if there are pinholes caused by dust or flakes during the process of forming the insulating film, the two layers The metal layer will be electrically shorted.

Means for Solving the Problems The present invention has a structure in which the drain electrode in a broad sense, which is electrically connected to the drain electrode, has at least two types of thin films in the portion where it overlaps with the gate wiring.

For example, a semiconductor layer may be selectively formed in addition to the first insulating layer, resulting in a two-layer structure, or a layered structure in which a second insulating layer is also added to these 2N layers. Further, when two or more types of insulating films having different components and etching characteristics (type of etchant, etching rate) are used as the first insulating layer, this first insulating layer may be used. Furthermore, in addition to the conventional example, various means can be considered, such as forming a third insulating layer to create a structure having first and third insulating layers.

By implementing the above-mentioned means, the first
By protecting the insulating layer (if this first insulating layer consists of several layers, the layer that comes into contact with the gate wiring) from direct contact with liquid or gas, the gate wiring steps can be protected. Chemical resistance has been greatly improved, and by forming the film with multiple layers, pinholes caused by flakes, dust, etc. during film formation are greatly reduced. Therefore, a TFT array having a dore's eye shape in a broad sense will be explained.

The parts with the same function are given the same number.

First, as shown in FIGS. 2(a) and 3(a), a first conductive layer 2, which will become a gate electrode and a gate wiring, is selectively formed on an insulating substrate 1 (for example, made of NiCr).
/Au, Cr/MoSix, All, I
To, fat resistor polysilicon, etc.). Subsequently, a first insulating layer 3 (for example, SiOx, SiNx, 5i
OxNx, Ta0z, TiOx, TiNx.

A non-monocrystalline silicon compound semiconductor layer 4 (for example, hydrogenated amorphous silicon, hydrogenated microcrystalline silicon, polycrystalline sil) is deposited as a semiconductor layer.
SiIJ: 7 germanium compound, silicon tin compound, silicon fluorine compound, silicon chlorine compound, silicon carbide, or a film containing a small amount of impurities such as P, N, or Q) is deposited, Second
Next, as shown in FIG. 2(a) and FIG.
After the PT is completed, a second insulating layer 6' and 16' is applied to at least two places above the gate wiring at the part that will become the channel and the part that will become one of the electrodes forming Cadd in Figure 2).
After selectively forming the non-single crystal silicon compound semiconductor layer 4 to expose the non-single crystal silicon compound semiconductor layer 4, an impurity (P) is added.

B, As, All, etc.) is deposited, and as shown in FIG. An island-shaped non-single-crystal silicon compound semiconductor including a portion where the compound semiconductor layer 4 is sequentially and selectively removed using a mixed solution of hydrofluoric acid and nitric acid, and the second insulating layers 6' and 15' are left. At least layers 4' and 14' and non-monocrystalline silicon compound layers 6' and 16' are formed.

Here, while etching the non-single-crystal silicon compound layer 6 and the non-single-crystal silicon compound semiconductor layer 4 containing impurities with the mixed solution such as hydrofluoric acid and nitric acid, the second insulating layer does not completely disappear. In this case, do not cover the upper part of the gate wiring which will become one electrode constituting the Cadd in Figure 2 with a resist (as shown in Figure 6 (→ It can be formed as follows.

In addition, the step of depositing the second insulating layer 5 in FIG. 3 (→) and the step of depositing the second insulating layer 6' and
If the step of selectively forming `` is omitted, it can be formed as shown in FIG. 6(b).

By the way, the island-shaped non-single crystal silicon compound semiconductor layer 4
' and 14' and single crystal silicon compounds 6' and 16', a transparent conductive film 7 (for example, I T O, S n O2
By selectively forming a tI n203t Au, etc.) across the gate wiring, the Cad
d can be produced. Next, although not shown in the diagram, the gate allocation is $2'! rAn opening is formed to take it out to the outside. Next, as shown in FIG. 3, the step at the edge of the gate wiring is large and the transparent conductive film 7 may be electrically disconnected, so a second conductive layer 10 is selected to cover at least a portion of this step. At the same time, in the TFT section, a second conductive layer is selectively formed to form a pair of drain electrode 8, source electrode 9, and source wiring 9 so as not to form an offset gate structure.

After that, using the drain electrode 8, source electrode 9, and source wiring 9 as masks, a non-single crystal silicon compound layer 6' containing the TPT channel portion and other exposed impurities is formed.
are removed to form 26' and 36'.

Here, the first insulating layer 3 may be composed of two or more layers having different components, and two or more kinds of insulating layers having different manufacturing conditions are stacked on the periphery. In this case, as shown in Figure 6 (→), C
By selectively forming only the first insulating layer made of several layers above the gate wiring in the portion that will become one electrode constituting the add, the effect of the present invention is also in the optical component.

Note that the second insulating layer in this example is not necessarily necessary for manufacturing the TPT, and the second insulating layer shown in FIG. 3(a) and the second insulating layer shown in FIG. If the step of selective formation is omitted, the schematic cross-sectional view shown in FIG. 1 is completed.

Further, each layer described in this embodiment may be composed of several layers of a plurality of types.

Further, the source/drain electrodes 8.9 described in this embodiment may be composed of the transparent conductive film 7, and the second conductive layer 10 in the stepped portion constituting Cadd is not necessarily required.

Furthermore, in this embodiment, the transparent conductive film covers the gate wiring, but it is only necessary that there be a portion that overlaps with the gate wiring. Further, the portion overlapping with the gate wiring need not necessarily be a transparent conductive film, but may be a second conductive layer as shown in FIG. 4(-).

Effects of the Invention In the TF array, if the electrodes constituting the Cadd shown in FIG. 4(b) are short-circuited, the drain voltage of the TPT will not reach the desired value, and this unit picture element will become defective. Further, it is thought that this may have some kind of adverse effect on the gate wiring forming the Cadd, although it varies depending on the driving method.

By the way, there are currently about five unit picture elements in a TFT array as shown in Fig. 2, and if the number of unit picture elements increases from 15 to 1 million in the future, the effect of the present invention will increase. is extremely large. For example, in a TFT array having 60,000 unit picture elements, 80 to 100 unit picture elements have conventionally become electrically defective.
In the case shown in FIG. 3(a), an average of 10 or less unit picture elements are electrically defective. It has been revealed that the causes of this are all located elsewhere and are not caused by an electrical short circuit in the Cadd section.

Considering the above, the yield in production can be greatly improved, and therefore costs can be reduced.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a unit pixel in a TFT array according to an embodiment of the present invention, FIG. 2(a) is a plan view of a unit pixel portion, and FIG. 3(a) to (→ are process sectional views of the TFT array of the present invention, FIG. 4(a) is a schematic plan view of a conventional unit pixel, and FIG. 4(b) is the same figure (→ circuit diagram, 6(a) to 6(d) are process diagrams of a conventional TFT array, and FIGS. 6(a) to 6(C) are process diagrams of another embodiment of the present invention. 2... Gate Wiring and gate electrode, 3...
...Insulating layer, 7...Transparent conductive film, 10...
...conductive layer, 14'...semiconductor layer 16/,
...Insulating layer, 16'...Non-single crystal silicon compound containing impurities. Name of agent: Patent attorney Toshio Nakao and 1 other person f-
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Claims (5)

[Claims] (1) A first conductive layer that becomes a gate electrode and a gate wiring is selectively formed on an insulating substrate, and a non-conductive layer is formed on the insulating substrate containing the first conductive layer via the first insulating layer. A single crystal silicon compound semiconductor layer is selectively formed, and a second conductive layer formed on the non-single crystal silicon compound semiconductor layer so as not to overlap with the first conductive layer is used as a source electrode/drain electrode. The second conductive layer constituting the drain electrode includes at least a transparent conductive film or is electrically connected to at least the transparent conductive film, and the drain electrode including the transparent conductive film also includes the transparent conductive film. A thin film transistor array having at least two types of thin films in a portion overlapping with a gate wiring that is a first conductive layer. (2) The drain electrode including the transparent conductive film is connected to the first
2. The thin film transistor array according to claim 1, comprising at least two types of insulating films in a portion overlapping with a gate wiring which is a conductive layer. (3) The drain electrode including the transparent conductive film is connected to the first
2. The thin film transistor array according to claim 1, comprising at least two layers of insulating films and one layer of a non-single crystal silicon compound semiconductor film in a portion overlapping with a gate wiring which is a conductive layer. (4) A first conductive layer that becomes a gate electrode and a gate wiring is selectively formed on an insulating substrate, and a non-conductive layer is formed on the insulating substrate including the first conductive layer via the first insulating layer. A crystalline silicon compound semiconductor layer is selectively formed, and a pair of impurity-containing amorphous silicon compound layers formed on the non-single crystal silicon compound semiconductor layer so as not to partially overlap with the first conductive layer. and a second conductive layer are used as a source electrode and a drain electrode, and at least a second insulating layer is formed on the non-single-crystal silicon compound semiconductor layer in a portion that will become a channel portion of the thin film transistor, forming the drain electrode. a second conductive layer containing at least a transparent conductive film, or at least the transparent conductive film is electrically connected to the gate, and a drain electrode including the transparent conductive film is the first conductive layer; A thin film transistor array having at least two types of thin films in a portion overlapping with wiring. (5) Under a part of the drain electrode including the transparent conductive film, the impurity-containing non-single-crystal silicon compound layer, the second insulating layer, the non-single-crystal silicon compound semiconductor layer, and the first 5. The thin film transistor array according to claim 4, comprising an insulating layer and a gate wiring which is the first conductive layer.