JPS6216548A - Semiconductor package structure - Google Patents

Abstract

PURPOSE:To obtain a highly reliable semiconductor package structure as well as to enable to easily build its water-cooled structure by a method wherein the first dielectric substrate with the semiconductor base is integrally formed with the second dielectric substrate, and also the material thereof shall be a sintered body of an Al nitride (AlN) film. CONSTITUTION:A dielectric substrate 12 for support and wiring comprising conductive paths 11, gold-metallized electrodes for an Si chip 1, and wire-bonding electrodes (substrate side) 13, is prepared. Then the gold film adhered on the back surface of the Si chip 1 is heated down into a gold-Si eutectic solder used as a die-bonding member 2 to bond the Si chip 1 at the prescribed position on the dielectric substrate 12 for support and wiring. The wire-bonding electrodes (chip side) 15 as many as the wire-bonding electrodes (substrate side) 13 are already formed on the surface side of the Si chip 1 and the mutually corresponding wire-bonding electrodes are connected to one another using fine gold wires 14. Lastly a cap member 9 is boned on the dielectric substrate 12 for support and wiring using cap bonding members 8.

Description

Detailed Description of the Invention (Field of Application of the Invention) The present invention is directed to fixing a semiconductor substrate to a first dielectric substrate, and electrically coupling the semiconductor substrate to the outside at the outer peripheral portion of the first dielectric substrate. The present invention relates to a semiconductor package structure mechanically coupled to a second dielectric substrate on which a group of terminals for
A first dielectric substrate on which a semiconductor substrate is fixed is integrated with a second dielectric substrate on which a group of terminals for electrically connecting the semiconductor substrate with the outside are arranged on the outer periphery, and the material of the second dielectric substrate is nitrided. The present invention relates to a semiconductor package structure that is a sintered body of aluminum.

(Background of the Invention) Semiconductor integrated circuits have become increasingly dense and highly integrated in recent years, and LSI chips have shown a remarkable tendency to become larger, and at the same time their heat generation density continues to increase.

In order to cope with such a situation, significant improvements are required in the structure and materials of semiconductor packages for connecting LSI chips to external circuits.

The so-called pin grid array, which has been attracting attention in recent years, was developed in response to the above situation.

The configuration of a typical pin grid array is shown in FIG. The main parts of the pin grid array are roughly divided into three parts, as shown in FIG.

The first portion 3 serves to mechanically support the LSI chip 1 and to efficiently release heat generated by the LSI chip.

The second part 7 supplies power to the LSI chip 1 and
Signals are taken out from the SI chip through a conductive path 11 formed inside the SI chip.

The third portion 9 is a lid for shielding the LSI chip 1 from the outside world.

These three parts 3, 7.9, when integrated as shown in FIG. 2, together form an airtight container. This container functions to isolate the LSI chip 1 from the outside world and maintain its performance at all times regardless of the state of the outside world.

Note that, in FIG. 2, air cooling fins 5 are fixed to the first portion 3 via adhesive members 4. As shown in FIG.

Further, the third portion (cap member) 9 is fixed to the second portion 7 by a cap adhesive member 8 .

The conductive path 11 is provided with a pin 10 for external connection.

The requirements for the materials of construction of the pin grid array are different for each of the three parts mentioned above.

The first part 3 is a member that supports the silicon chip 1 fixed via the die bonding member 2, and this part 3
In order to efficiently dissipate the heat generated in the LSI chip 1, high thermal conductivity is required, and in order to ensure reliability of adhesion with silicon (St), a coefficient of thermal expansion close to St is required, and system design. Electrical insulation is desired to ensure flexibility.

This first portion 3 includes a conventional Be IJ (Be0).

Alumina (Al2O,), copper-tungsten alloy (Cu
-W) etc. have been used.

The second part 7 is a member for supporting and wiring the first part 3, and a single layer or multilayer wiring is provided here, and the second part 7 is connected to the first part 3 via an adhesive member 6. 3 is fixed with adhesive.

Therefore, in this second portion 7, it is necessary to form the conductive paths 11 at a high density, and a material capable of high-density multilayer wiring is required. Conventionally, alumina, beryllia, etc. have been used for this second portion 7.

The third part 9 is the first part 3 and the second part 7.
It is a cap or lid member that closes the recessed part (in which the silicon chip 1 is housed) formed by the second part 7, and the compatibility of the thermal expansion coefficient with the second part 7 is determined by its constituent material IK.
This is a required quality. Copal (Fe-29Ni-17Co), alumina, etc. have been used for the third portion 9.

Furthermore, when these three parts 3 and 7.9 are integrated, it is desirable that the coefficients of thermal expansion of these three parts be close to each other in order to ensure reliability as a whole package. .

As mentioned above, the first part 3 must have a coefficient of thermal expansion close to %Si, so the second part 3. It is desirable that the material constituting the third portions 7, 9 also have a coefficient of thermal expansion close to that of St.

Here, the characteristics and drawbacks of each of the above materials will be described. 1st, 2nd and 3rd semiconductor devices that do not require particularly high performance
The material often used for parts 3, 7.9 is alumina. The biggest reason for this is that alumina is cheap.

However, alumina has a coefficient of thermal expansion of 6.5.
Not only does it have a large coefficient of thermal expansion that does not match that of silicon, but also has a low thermal conductivity (17W/
mK).

Among these drawbacks, beryllia is used to improve the thermal conductivity and improve the performance of semiconductor devices. Since the thermal conductivity of beryllia is as high as 260 W/mK, if beryllia is used in the first portion 3, the heat-generating corrosion can be significantly increased even with the same package size.

However, beryllia is expensive and has a low coefficient of thermal expansion? , 5
Not only does it have a large coefficient of thermal expansion of X 10, and its coefficient of thermal expansion does not match that of silicon, but it also has the major drawback of being toxic.

If it is not necessary to electrically insulate the LSI chip l and the outside of the package, the material for the first portion 3 may be
An alloy of copper and tungsten (Cu-W) is used.

(For example, the thermal conductivity of the tungsten 20% alloy used is 280 W/m・0, which is almost the same as beryllia and silicon carbide (SiC) and is sufficiently large. However, the coefficient of thermal expansion is 7. OX, comparable to alumina.
10, which does not match with silicon.

As mentioned above, the materials that have been used in practice include
There is no product that can satisfy the required performance in all aspects. In particular, Berria is the only material that has a high thermal conductivity and can be used for high-performance semiconductor devices, and Berria is toxic, so an alternative material has been desired.

Examples of materials that meet these demands include:

Nikkei Electronics September 24, 1984 issue pp.2
Silicon carbide was developed as disclosed in ``65-294@SIC Ceramic, whose application to LSI packaging has begun.''

Silicon carbide has a thermal conductivity of 270 W/mK, which is based on Veryrif, and a coefficient of thermal expansion of 3.7X1, which is close to that of silicon.
0, and it also has the great feature of being non-toxic.

However, silicon carbide has a problem in that it cannot be used as a material for second portion 7 because its sintering temperature is too high and multilayer wiring cannot be formed. Also.

Silicon carbide has a thermal expansion coefficient that does not match that of alumina, which is normally placed on the side of second portion 7, so there is also the problem that the bonded portion with alumina, that is, second portion 7, cannot have sufficient reliability.

As mentioned above, silicon carbide also has insufficient performance as a material for pin grid arrays.

(Object of the Invention) An object of the present invention is to fix a semiconductor substrate to a WJl dielectric substrate, and to attach a group of terminals to the outside 111 of the first dielectric substrate for electrically coupling the semiconductor substrate to the outside. 2nd f placed
To provide a semiconductor package structure mechanically coupled to an Is electric substrate, which eliminates the drawbacks of the above-mentioned constituent materials and integrates the first and second dielectric substrates. It is.

(Summary of the Invention gI) The present invention provides a first dielectric substrate on which a semiconductor substrate is fixed, and a second dielectric substrate on which a group of terminals for electrically connecting the semiconductor substrate with the outside are arranged on the outer periphery. It is unique in that it is integrated and its material is a sintered body of aluminum nitride (AJN).

Since aluminum nitride has a coefficient of thermal expansion of 3.4×10 −′, which is close to that of silicon, the reliability of the bonded portion with the silicon chip 1 is sufficiently high.

Furthermore, aluminum nitride has a thermal conductivity of 149 W/m
・As shown in Table 1, it has a relatively large value of 0, which is as good as when using beryllia or SIC.
Low thermal resistance can be obtained.

Table 1 (Note): The thickness of each material is 0.6 mm. The thickness of the silicon chip is 0.5 mm. The connection between each material and the silicon chip is gold-tin solder. The thermal resistance referred to here is: When the silicon chip 1 is energized and the temperature of the silicon chip 1 is sufficiently stabilized. It is the quotient obtained by dividing the difference between the surface temperature of the silicon chip 1 and the bottom temperature of the dielectric substrate supporting it by the amount of heat generated by the silicon chip 1.

The thermal resistance shown in Table 1 is based on titanium (Ti) on the surface of the dielectric substrate in order to bond the silicon chip 1 to the dielectric substrate.
) - Platinum (Pt) - Gold (Au) vapor deposited film is formed. Table 1 shows the data when the surface of the dielectric substrate is metallized by molybdenum (Mo) printing. The thermal resistance increases by approximately 0.1°C/W for all dielectrics.

In other words, when silicon carbide, which has the lowest thermal resistance in Table 1, is metallized by printing molybdenum (Mo) (thick film metallization), aluminum nitride has titanium (Ti).
-Thermal resistance is worse than when metallization (thin film metallization) is performed by vapor deposition of platinum (Pt) and gold (Au).

This shows that the thermal conductivity of aluminum nitride is both necessary and sufficient as a component material for semiconductor packages, and that when high performance is required, it is more effective to improve the metallization than to change the substrate material. ing.

One of the important reasons why aluminum nitride is suitable as a constituent material for semiconductor packages is that aluminum nitride is suitable for metallizing high-performance thin films (for example, films formed by vapor deposition). The reason why thin film metallization is hardly applied to other dielectric substrates, such as alumina ceramics, is of course due to cost issues, but rather,
Thin film metallization is not suitable for general ceramics such as alumina in terms of reliability.

Thin film metallization has a multilayer structure with a total film thickness of about 1 μm. Therefore, the surface on which the film is formed is required to be as smooth as possible. If the film is not smooth, the film will break at the stepped portion, and layers other than the outermost layer of the multilayer structure will appear on the surface, resulting in phenomena that impair reliability, such as reacting with solder.

Typical ceramics contain impurities (additional elements) in their raw materials and require auxiliary agents during sintering, so even if they are polished to a mirror surface, angular irregularities on the order of microns remain on the surface. Therefore, it is not suitable for thin film metallization.

However, aluminum nitride has a highly pure raw material powder and does not contain any additive elements, and does not require a sintering aid. Furthermore, since the particle size of the raw material powder is fine and uniform at approximately 0.6 μm, the surface after sintering at approximately 1800°C exhibits gentle undulations of approximately 5 μm without any special processing.
As already mentioned, it is suitable for thin film metallization with low thermal resistance and clearly higher performance than thick film.

Moreover, since aluminum nitride has a low sintering temperature and can be used for multilayer wiring, the second part 7-- in FIG.
That is, it can also be used as a support and wiring member.

(Example of the invention) An embodiment of the present invention will be described with reference to FIG.

In this embodiment, the first part (IC support member) 3 in a general pin grid array as shown in FIG.
and a second part (wiring member) 7 are integrated to form a support and wiring dielectric substrate 12, and this part is made of aluminum nitride, one side (lower side in the figure) is formed into a step shape in advance, and the interior is It is sintered with a plurality of conductive paths 11 formed therein.

Furthermore, the back surface (top (III) in the figure) is made thinner in areas other than the area where the silicon chip 1 is bonded in order to save material.

The area to which the silicon chip 1 is bonded has a − side of approximately 10
mm square, and the center part is 7 mm square (silicon
(same dimensions as the chip 1) is coated with gold metallization for adhesion of the silicon chip 1.

Furthermore, the part molded in one step shape, that is, the silicone
At the periphery of the area where the chip 1 will be glued.

It was connected to the internal conductive path 11. Wire bonding electrodes (substrate side) 13 made of gold metal are formed in a number corresponding to the number of conductive paths 11.

Book 5I! In the embodiment, the third portion or cap member 9
The material was Kovar (Fe-29Ni-17Co). Copal has a coefficient of thermal expansion of 4.5X10-'
And it's close to that of silicon.

° Therefore, in this example, all of the constituent wave phases of the semiconductor package structure repair have thermal expansion coefficients close to that of silicon, and thermal fatigue due to differences in thermal expansion coefficients between members can occur in any part of the package. No problems occur. In addition, in this embodiment, the supporting portion of the silicon chip 1 (the first part in FIG.
Since the supporting and wiring parts (corresponding to the second part 7 in the 1EZ diagram) are integrated, the number of connection fixing parts is reduced by one, and an improvement in reliability can be expected.

To obtain the semiconductor package structure according to the present invention, first, a conductive path 11 is formed inside, gold metallization is applied to the silicon chip 11, and a wire bonding electrode (substrate side) 1 is formed.
A dielectric substrate 12 for support and wiring on which 3 is formed is prepared.

Next, the gold film adhered to the back side of the silicon chip 1 is
The support is transformed into gold-silicon eutectic solder by heating and used as the die bonding member 2.

A silicon chip 1 is placed at a predetermined position on the dielectric substrate 12 for wiring.
Glue 1.

The same number of wire bonding electrodes (chip side) 15 as the wire bonding electrodes (substrate side) 13 are formed on the surface side of the silicon chip l, and thin gold wires are connected between the corresponding wire bonding electrodes. wire 1 which is
Connect with 4.

Finally, the third part, ie the cap member 9, is made of gold.
the support with a cap adhesive member 8 made of tin eutectic solder;
Adhere to the dielectric substrate 12 for wiring.

A semiconductor package structure according to the present invention is completed.

As a modification of this embodiment, a structure may be considered in which the part @3, that is, the cap member 9, is made of the same aluminum nitride as the supporting and wiring dielectric substrate 12.

In this case, since all the constituent materials except the silicon chip 1 are the same, reliability against thermal fatigue is further increased. However, on the other hand, aluminum nitride is more expensive than copper, so it is disadvantageous in terms of cost.

Also, an adhesive member 8 for the die bond member 2 and the cap 9
The solder material does not necessarily have to be the one used in this embodiment, and may be appropriately selected from common solder materials.

However, the melting point of the die bonding member 2 must be higher than the working temperature of the cap bonding member 8 (usually about 50° C. higher than the melting point). This is because the die bonding member 2 must not melt or soften when the third portion, that is, the cap member 9 is bonded.

The embodiment shown in FIG. 1 described above is an example in which the present invention is applied to the air-cooled semiconductor package structure shown in FIG. It is expected that air cooling will not be able to cope with this problem. Therefore, it becomes necessary to adopt a water-cooled structure.

FIG. 3 is a sectional view showing the main structure when the present invention is applied to a water-cooled semiconductor package structure. In the case of a water-cooled structure, the silicon chip 1 and the cooling water must be electrically insulated.

Aluminum nitride is an insulator and has good workability, so it is used in the region of the support and wiring dielectric substrate 12 for dissipating heat from the silicon chip 1, as shown in the figure.
It is easy to make holes 16 for water cooling. This hole 16
, connect the water cooling pipe 18 through the joint 17,
By passing the coolant, the silicon chip 1 can be efficiently cooled.

(Effects of the Invention) As is clear from the above description, the semiconductor package structure of the present invention includes a first dielectric substrate to which a semiconductor substrate is fixed, and a peripheral portion that connects the semiconductor substrate electrically to the outside. The second dielectric substrate on which the terminal group for bonding is arranged is made of the same material and has an integral trap structure, and since the material is a sintered body of aluminum nitride, the thermal resistance is low and the heat dissipation is good. A semiconductor package structure that is not only good but also highly reliable is obtained because the number of connecting parts is reduced and the difference in coefficient of thermal expansion at the connecting parts is substantially constant.

Furthermore, aluminum nitride has good workability, so
It is also easy to create a water-cooled structure by forming holes 16 for coolant passage in a portion of the dielectric substrate 12 for support and wiring that serves as a support for the silicon chip 1.

[Brief explanation of drawings]

FIG. 1 is an enlarged sectional view of essential parts showing an embodiment of the present invention, FIG. 2 is a partially sectional perspective view showing an example of a conventional counterfeit semiconductor package, and FIG. 3 is a perspective view of another embodiment of the present invention. FIG. 3 is an enlarged cross-sectional view of main parts.

Claims (6)

[Claims] (1) A semiconductor substrate is fixed to a first dielectric substrate, and the first dielectric substrate is attached to a second dielectric substrate having a group of terminals arranged on the outer periphery for electrically coupling the semiconductor substrate to the outside. In a mechanically coupled semiconductor package structure, the first
and a semiconductor package structure characterized in that the second dielectric substrate is a dielectric substrate for supporting and wiring that is made of substantially the same material and is integrally constructed, and the material is an aluminum nitride sintered body. body. (2) A conductive path for electrically connecting the semiconductor substrate and the terminal group is formed in a portion of the supporting and wiring dielectric substrate corresponding to the second dielectric substrate. A semiconductor package structure according to claim 1, characterized in that: (3) A hole for passing a coolant is formed inside a portion of the supporting and wiring dielectric substrate corresponding to the first dielectric substrate. The semiconductor package structure according to item 1 or 2. (4) The supporting and wiring dielectric substrate is configured such that a portion corresponding to the first dielectric substrate is a recessed portion, and the semiconductor substrate is fixed to the bottom surface of the recessed portion. A semiconductor package structure according to any one of claims 1 to 3. (5) The semiconductor package structure according to claim 4, wherein the recessed portion is sealed by a cap member. (6) The semiconductor package structure according to claim 5, wherein the material of the cap member is aluminum nitride.