JPS6216558A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To simplify the manufacturing process by forming a base region of a bipolar transistor and a source and drain regions of a MOS transistor in the same process. CONSTITUTION:Antimony or arsenic is selectively doped in a P-type single crystalline silicon substrate 1 to form N-type embedded regions 2 and 21, and boron is selectively doped to form P-type embedded regions 3 and 31. Then, an N-type silicon epitaxial layer 4 is grown on the whole surface and boron is selectively doped to form a separating region 5 on the P-type embedding region 3 and a P-type well region 6 on the P-type embedding region 31 for forming an N-channel MOS transistor. Then, a thick silicon oxide film 7 is formed by selective oxidation method. And a thin silicon oxide film 8 and a gate electrode 9 such as polysilicon are formed. Then, an emitter region 13, a collector contact region 14, a bottom gate contact region 18, a source region 18 and a drain region 151 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit in which a bipolar transistor and a MOS (MOS) transistor are formed within the same semiconductor substrate.

Conventional technology bipolar transistor and 0MO8 (complementary MO5))
A conventional semiconductor integrated circuit in which transistors are integrated in a single semiconductor substrate has been formed according to a process flowchart as shown in FIG. The structure of a conventional semiconductor integrated circuit and its manufacturing method will now be described with reference to FIG.

First, an n-type silicon epitaxial layer 4 is formed on a p-type single crystal silicon substrate 1 in which an n-type buried region 2.21 and a p-type buried region 3.31 are selectively formed, and a p-type impurity is diffused. A p-type isolation region 5 is formed above the p-type buried region 3, and a p-well region 6 is formed above the p-type buried region 31. After that, a thick silicon oxide film 7 is formed in the region where the MOS transistor is to be formed by selective oxidation, and then the MOS transistor is formed on the surface.
) A thin silicon oxide film 8 is formed to serve as a gate oxide film for the transistor, and a conductive film such as polysilicon is selectively formed thereon to form a gate electrode 9. In addition,
In the figure, the regions indicated by M, B, and C are NPN transistors, P-channel MOS transistors, and N-channel MOS transistors.
This is a region where a 1/MOS transistor is formed. (Second
Diagram a).

Next, boron is ion-implanted selectively to form the source region 1o and drain region 101 of the region BKP channel/l/MO3I-transistor.

A guard band region 11 is formed between regions B and C. Source region 1o and drain region 101 formed by this process
The sheet resistance of is 50-150Q10 (Fig. 2b)
).

Further, boron ions are selectively implanted over a large area to form the base region 12. The sheet resistance of this base region 12 is 200 to 120% higher than the sheet resistance of the source and drain regions of a P-channel MOS transistor, with the intention of realizing high-speed bipolar transistors.
It is set to oooΩ/mouth. (Figure 2C).

Next, arsenic or phosphorus is ion-implanted selectively to form an emitter region 13 and a collector contact region 14 in the region M, and also to form a source region 16 and a drain region 161 of the transistor in the region Ci/CM channel MO8). (Figure 2d).

Finally, after forming a PSG film 16 serving as an interlayer insulating film on the surface, a contact window is opened and an aluminum electrode 17 is formed in this portion (FIG. 2e).

Problems to be Solved by the Invention In this conventional manufacturing method, P-channel MO8)
The boron ion implantation is separated to make the sheet resistances of the source and drain regions of the transistor and the base region of the NPH transistor different. Therefore, there is a problem in that the manufacturing process of the semiconductor integrated circuit becomes complicated.

Means for Solving the Problems The method of manufacturing a semiconductor integrated circuit of the present invention includes the step of separately forming first and second regions of opposite conductivity type on a semiconductor substrate of -conductivity type. , after forming a gate oxide film on the surface of the semiconductor substrate, forming a gate electrode on the gate oxide film located on the second region; - Step of ion-implanting conductive type impurities to form an emitter region with high impurity concentration, thermally oxidizing the surface of the semiconductor substrate, and selecting the thickness of a thin oxide film equivalent to the gate oxide film covering the emitter region. and a step of ion-implanting impurities of the same conductivity type as the semiconductor substrate to form a base region in the first region and source and drain regions in the second region. It is prepared.

Operation: According to this manufacturing method, the base region of the bipolar transistor and the source and drain regions of the MO5I transistor can be formed in the same process.

The base region can also be a so-called graft-based structure, comprising an active base region and a base contact region.

Embodiment An embodiment of the method for manufacturing a semiconductor integrated circuit according to the present invention will be described with reference to the process flowchart of FIG.

First, antimony '
Alternatively, the n-type buried region 2 may be selectively doped with arsenic.
．． 21 is formed. Next, boron is selectively doped to form a p-type buried region 3.31. In addition, in the figure,
The regions indicated by B and C are regions for forming an NPN transistor, a P-channel MO8) transistor, and an N-channel MOS transistor, as in FIG.
),.

Next, an n-type silicon epitaxial layer 4 having a resistivity of 0.6 to 100 m is grown over the entire surface (FIG. 1b).

Thereafter, boron is selectively doped into the surface portion of the n-type epitaxial layer corresponding to the p-type buried regions 3 and 31, and an isolation region 6 connected to the p-type buried region 3 is formed on top of the p-type buried region 3.
A p-well region 6 for forming an N-channel MO transistor (8) is formed on the p-type buried region 31 (FIG. 1C).

Next, a thick silicon oxide film 7 is formed on the surfaces of regions B and C by zeta selective oxidation. Thereafter, the silicon oxide film is selectively removed to partially expose the silicon surface (FIG. 1d).

Subsequently, a thin silicon oxide film 8 to serve as a gate oxide film is formed on the surface, and a gate electrode 9 made of polysilicon or the like is further formed on this gate oxide film (FIG. 1, 6).

Next, after applying a resist film (not shown) to the surface, openings are made in predetermined areas of this resist film, and arsenic or phosphorus ions are implanted into the areas. shaped emitter area 1
3 and collector contact region 14 in region B?
a bottom gate contact region 18 of the shape, and a region C
A t-shaped source region 16 and a drain region 161 are formed (FIG. 1f).

Next, the surface of the substrate is oxidized using a thermal oxidation method. By the way, the above-mentioned ♂ type diffusion regions 13, 14, 16, and 18 have a high impurity concentration, and the other regions are the n-type silicon epitaxial layer 4 with a low impurity concentration.

The higher the impurity concentration, the faster the oxidation rate of the silicon substrate.
Therefore, a silicon oxide film 8 is formed on the n+ type diffusion regions 13, 14, 16, and 18 to a thickness greater than that on the n type silicon epitaxial layer 4.

Subsequently, after applying a resist film, openings are made in predetermined regions of the resist film, boron ions are implanted, and the base region 12 is formed in region B, and the source region 1° and the source region of the P-channel MO8 transistor are formed in region B. A drain region 101 is formed, and a guard band region 11 is formed between regions B and C (FIG. 1g).

Note that the thickness of the silicon oxide film on the emitter region 13 is larger than the thickness of the surrounding silicon oxide film, and when the base is formed, the active base region directly under the emitter has a low impurity concentration, and the base around the emitter region A graft base structure is formed in which the contact region has a high impurity concentration. On the other hand, since the thickness of the silicon oxide film on the source region 1o and drain region 101 of region B is smaller than the thickness of the silicon oxide film on the emitter region 13, the impurity concentration of the source region and the drain region is lower than that of the active base region. can also be made higher.

Finally, after forming the PSG film 16 which will serve as an interlayer insulating film,
A contact window is opened and aluminum electrode 1 is placed in this area.
7 (Fig. 1 h).

Effects of the Invention According to the method for manufacturing a semiconductor integrated circuit of the present invention, NPN
) A base region that can increase the current amplification factor of the transistor and reduce the base spread resistance, and a p-channel M
The source region and drain region, which can reduce the on-resistance of the OS transistor, can be formed in the same process, which simplifies the manufacturing process and has a large economical effect.

[Brief explanation of the drawing]

Fig. 1 is a process flow chart showing a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention, and Fig. 2 is a process flow chart showing a conventional method for manufacturing a semiconductor integrated circuit. Substrate, 2.21...N-type buried region, 3.31...P-type buried region, 4...
...N-type silicon epitaxial layer, 6...
Separation region, 6...p well region, 7...
・Thick silicon oxide film, 8... Silicon oxide film, 9... Gate electrode, 10... Source region of P channel MOS transistor, 101...
...Drain region of P-channel MOS transistor, 11... Cart band region, 12...
...Base region, 13...Emitter fillt
14... Collector contact area, 16...
...N-channel MO8) Source region of transistor,
161...Drain region of N-channel MOS transistor, 16...PSG film, 17...
...Aluminum electrode, 18...P-channel MO8) Bottom gate contact region of transistor. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 Figure 1 Figure 2 Figure C%3 group

Claims (1)

[Claims] A first semiconductor substrate of an opposite conductivity type is placed on a semiconductor substrate of one conductivity type.
and a step of separately forming a second region, and forming a gate oxide film on the surface of the semiconductor substrate, and then forming a second region.
forming a gate electrode on the gate oxide film located on the first region; and forming an emitter region with a high impurity concentration by ion-implanting impurities of the same conductivity type as the first region into the first region. a step of thermally oxidizing the surface of the semiconductor substrate to selectively increase the thickness of a thin oxide film equivalent to a gate oxide film covering the emitter region; and ion implantation of impurities of the same conductivity type as the semiconductor substrate. and forming a base region in the first region and forming source and drain regions in the second region.