JPS6216618A - Encoder - Google Patents

Abstract

PURPOSE:To shorten a variation point detection processing time by executing a variation point detection processing by a picture element unit before an encoding processing, after a memory output, in case when it has been detected that an image signal has a variation point within a range of a prescribed length before a memory input. CONSTITUTION:An image signal which is inputted from an input part 1 detects whether a variation point exists in an input signal of a length which has been determined in advance or not, by a memory pre-stage variation point detecting part 31, and in case said point exists, this signal is accumulated in a detecting signal accumulating part 34. An encoding processing part 4 counts up a read address counter 36 by one address each within a range in which it has been transmitted that the variation point exists in its range, by the detecting signal accumulating part 34, makes a memory post-stage variation point detecting part 35 detect the variation point by a picture element unit, and counts up in order to skip over its range within a range in which the variation point does not exist.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an encoder used in a facsimile machine or an image storage device that handles nine image information as an electrical signal quantized into binary levels of "Oj and 1". Regarding.

In particular, the present invention relates to an encoder that has a memory before an encoding processing unit and converts a continuous run length of "0" or "1#" into a code.

[Conventional technology]

Conventionally, in this type of encoder, data is changed from "0" to "1" only immediately before the encoding processing section, that is, at the rear stage of the memory.
' or a change point from "1" to "10" was detected.

[Problem that the invention seeks to solve]

This is because, in the conventional encoder described above, change point detection of the binarized image signal is uniformly performed only at the front stage of the encoding processing unit, that is, at the rear stage of the memory.

Even when no changing points appear over a wide range, the same changing point detection processing as when changing points frequently appear is performed.

Therefore, the processing time for detecting a change point in a portion of one image signal where the change point does not appear over a wide range is required.

Regarding the processing time of parts where changing points frequently appear.

The disadvantage is that it cannot be significantly shortened.

[Means and operations for solving the problem] The encoder according to the present invention has a circuit for detecting a change point between the input section before the memory and the memory, and between the memory and the encoding processing section,
The change point detection section in the front stage of the memory detects whether the image signal consisting of KO# and "1'" has a change point within an arbitrary length range.

If there is a change point within a range of arbitrary length, change point detection processing is performed pixel by pixel in a change point detection section located after the memory.

〔Example〕

Hereinafter, nine embodiments of the present invention will be described in detail with reference to the drawings.

The figure is a block diagram showing the configuration of an embodiment of an encoder according to the present invention.

The input unit 1 is for inputting a binary image signal to an encoder, and is generally an image reading device or the like.

The image signal inputted from the input section 1 is stored in the memory 2, and at the same time, is subjected to change point detection processing by the pre-memory change point detection section 31 in the change point detection circuit 3. When the memory pre-stage change point detection unit 31 detects a change point, it outputs a detection signal to the detection signal latch unit 32, and the detection signal latch unit 3 outputs a detection signal to the detection signal latch unit 32.
2 holds the detection signal. Next, when the write address counter 33 performs count amplification and the memory 2 takes in an input signal of a predetermined length, the detection signal storage section 34
stores the output signal of the detection signal launch section 32 and clears the detection signal latch section 32. More than.

This is a series of operations related to the memory pre-stage change point detection unit 31.
The same processing is sequentially performed for input signals of any predetermined length that are input from the input unit 1 thereafter.

Next, the operation of the memory post-change point detection section 35 will be described. First, the read address counter 36 indicates the start address of the memory 2, and the memory 2 outputs the first; At the same time, the read address counter 36 indicates the start address of the detection signal accumulation section 34, and the detection signal accumulation section 34 receives a signal indicating whether there is a change point in the initial input signal of any predetermined length. is output to the encoding processing section 4. If there is no change point at this time, the encoding processing unit 4 knows that there is no change point within a predetermined arbitrary length range.

The signal storage unit 34 detects the next input signal of any predetermined length from the memory 2 and detects a signal indicating whether or not there is a change point in the next input signal of any predetermined length. A signal is output to the read address counter 36 to count up by a predetermined arbitrary length. If there is a change point, the read address counter 36 counts up one address at a time,
A signal is output from the memory 2 to the memory post-change point detection section 35, and change point detection processing is performed in units of two pixels.

The above is a series of operations related to the memory post-change point detection section 35, and is repeated thereafter until all input signals of the memory section 2 are read out.

〔Effect of the invention〕

As explained above, the encoder according to the present invention is as follows.

A change point detection circuit is provided between the image signal input section before the memory and the memory, and between the memory and the encoding processing section. It detects whether or not there is a change point, and only when there is a change point within the range, the change point detection unit in the subsequent stage of the memory performs change point detection processing in pixel units.9 When encoding the image signal, change inspection is performed. This has the effect of greatly shortening the output processing time.

[Brief explanation of drawings]

The figure is a block diagram showing the configuration of an embodiment of an encoder according to the present invention. 1... Input section, 2... Memory, 3... Change point detection circuit. 31...Memory front stage change point detection unit, 32...Detection signal latch unit, 33...Write address counter, 34
. . . detection signal storage unit, 35 . . . memory post-stage change point detection unit, 36 . . . read address counter, 4 .

Claims (1)

[Claims] 1. Has a memory in front of the encoding processing unit, which stores “0” and “1”
“0” or “1” of the signal represented by two levels of “
In an encoder that converts the length of a series of An encoder characterized by being provided with a circuit for detecting points.