JPS62168221A - Input and output controller - Google Patents

Abstract

PURPOSE:To perform the rerise of a system in a short time by securing such a constitution where an input/output controller recovers automatically the data broken when a power supply is cut off with no intervention of the host software. CONSTITUTION:When a previous notice is given from a power supply 4 via a voltage drop previously noticing line 202, a microprocessor 103 of an input/ output controller DKC2 receives an interruption. Then a DMA control circuit 101 is put under a saving mode during a writing action and the transfer of data is discontinued to a device control circuit 107. The data are transferred to an FIFO(2)101 only and the numbers of the unit, cylinder, track, sector, etc. of a magnetic disk device 3 are stored, and at the same time a data storing frag is stored when the power supply is cut off to an FIFO(1)110 after the end of the data transfer. When the power supply is recovered, the self-diagnosis is carried out and the data stored in the FIFO(2)111 are written and recovered based on the information on the FIFO(1)110.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input/output control device, and more particularly to an input/output control device that controls read/write operations of a magnetic disk device in accordance with instructions output from a central processing unit.

[Conventional technology]

In general, microprogram-controlled input/output control devices operate in response to commands output from a central processing unit. This command includes a write command and a read command.

Conventionally, when transferring data between a magnetic disk device and a central processing unit, when a command is issued from the central processing unit to a human output control device, the human output control device decodes this command and sends the necessary information to the magnetic disk device. It sends commands to control direct memory access data transfer and execute data transfer.

When the data transfer is completed, the input/output control device notifies the central processing unit of the completion of the operation through an interrupt.

With conventional input/output control devices, if the system power is cut off due to a momentary power outage or power outage during a write operation (data transfer from the central processing unit to the magnetic disk drive), as shown in Figure 7, the Since the write operation is interrupted midway before writing the specified data length, data in the sector being written is destroyed. Furthermore, when the power is turned off in both the central processing unit and the input/output control unit, all information about the operations being executed is cleared (disappeared).

[Problem that the invention seeks to solve]

The above-mentioned conventional input/output control device causes sector data to be destroyed due to a power outage such as a momentary power outage or power outage of the system that occurs during a write operation, and as a result, data is inadvertently destroyed when the power is restored. The disadvantage is that reading a sector that has been previously read will result in a read error, causing a system failure.

Also, in order to avoid the above-mentioned boarding error, it is necessary to perform file recovery before starting the system.
If the system software is stored on the magnetic disk drive that was being used, and the corrupted sector is part of a file directory, it will take a long time to recover the file, resulting in extended system downtime. be.

In view of the above-mentioned points, an object of the present invention is to provide an input/output control device that automatically restores sectors whose data has been destroyed due to a momentary power interruption or power outage in a system, without software intervention, after the power is restored. It is about providing.

[Means for solving problems]

The input/output control device of the present invention is an input/output control device that controls read and write operations of a magnetic disk device based on commands from a central processing unit, and includes a voltage monitoring circuit that monitors a voltage drop, and a voltage monitoring circuit that monitors voltage drops and operates when a voltage drop occurs. A first FI that stores information including the unit number, cylinder number, track number, sector number, voltage drop instruction flag, and data storage validity instruction bit of the magnetic disk device that was being used.
FO and a second FIF that can store a predetermined number of bytes of data
0, a battery circuit that backs up the first FIFO and the second FIFO with a battery, and an interrupt circuit that enables an interrupt to the microprocessor by driving a voltage drop warning line of a power supply of the system.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a configuration diagram showing an embodiment of the present invention. An input/output control device (hereinafter abbreviated as DKC) 2 of this embodiment is connected to a central processing unit (hereinafter abbreviated as CPU) 1 via a bus, and also includes a plurality of magnetic disk devices (
(hereinafter abbreviated as DKU) 3. Also,
The DKC 2 is connected to a power supply unit (hereinafter abbreviated as PWU) 4, and the PWU 4 is connected to the CPUI via a voltage drop warning line 202.

The DKC2 of this embodiment uses direct memory access (DKC2).
MA) control circuit 101, hash control circuit 102, microprocessor 103, interrupt circuit 104, power supply monitoring circuit 105, gate 106, device control circuit 1
07, a random access memory (hereinafter abbreviated as RAM) 108, a programmable read only memory (hereinafter abbreviated as FROM) 109, and a 111th memory having an 0MO3 structure for storing information etc. when the power is turned off.
FO (hereinafter referred to as FIFO (l)) 11O and 65K
The second FIFO (hereinafter referred to as FIFO) has a one-chip 0MO3 structure that can store data up to
21) 111 and F T F 0 (11110
and a battery circuit 112 that backs up F r F 0 (21111) with a battery.

Referring to FIG. 2, the battery circuit 112 includes a back amplifier battery B made of a nickel cadmium battery, a capacitor C1, resistors R1-R3, and transistors TI and T2. The positive and negative electrodes of the back amplifier battery B are P I F 0 (11110
and P I F 0 (connected to the operating voltage input terminal vCC and ground terminal GND of 21111, respectively. This battery circuit 112 is connected to the transistor T1
F I F by back amplifier battery B when off.
0(ll 110 and FIFO(21111) are battery backed up.

Referring to FIG. 3, the power supply monitoring circuit 105 includes a voltage detector 113, resistors R4 to R6, and a capacitor C2. Note that the reference numeral 201 indicates the power supply monitoring circuit 10.
5 to the microprocessor 1 via the interrupt circuit 104.
The emergency interrupt line connected to 03 is shown. In this power supply monitoring circuit 105, when the power supply voltage drops, the voltage detector 113 detects this and drives the emergency interrupt fa201.

Referring to FIG. 4, F I F 0 (11110) includes a voltage drop instruction flag indicating that there has been a voltage drop;
F I F 0 (2) A data storage validity indication bit (hereinafter abbreviated as V bit) indicating that data is stored in 111, the unit number of DKU3, and the cylinder number at the time of power-off. , the trunk number when the power is turned off, the sector number when the power is turned off, the cylinder number when the operation starts,
The track number at the start of operation and the sector number at the start of operation are stored. Note that the voltage drop instruction flag indicates that there has been a voltage drop when it is “1”.
When the V bit is “1”, F T F O(2+11
1 indicates that data is stored.

Referring to FIG. 5, the process in the DKC 2 of this embodiment includes a determination step 601 for determining whether writing is in progress.
and the clear step 602 of the device control circuit 107.
, an evacuation mode setting step 603 of the DMA control circuit 101, an emergency interrupt determination step 604, and a P I
A step 605 for determining the end of data transfer to the FOf2+ 111, a step 606 for storing necessary information such as a flag in the FTF(]11, a self-diagnosis step 60B,
F o (tl tio's chi,! Ivy step 609
, flag determination step 610 , V bit determination step 611 , write operation execution and P I F Of
l+ 110 clear step 612 and status H
IE step 613, command detection step 614 from CPUI, power-off status determination step 615,
It consists of a control information acquisition step 616, a parameter generation and entry step 617, a read/write operation step 618, an end determination step 619, and an end status editing step 620.

Next, the operation of the input/output control device of this embodiment configured as described above will be explained.

When DKC2 receives a write command from CPtJl,
Receives necessary control information from the CPUI and stores it in the RAM 108.
(step 616). Next, the parameters necessary for operation are generated and the address/count value is set in the DMA control circuit 101, and the unit number, cylinder number, trunk number, sector number, etc. are set in the device control circuit 107 (step 617). The circuit 101 and the bus control circuit 102 are activated to start DMA data transfer (step 618).

When a power failure occurs during a write operation, the voltage drop warning line 202 is driven as shown in FIG.
'r1. It is designed to drive the voltage drop warning line 202 at least 10m5 before the tX voltage +5VDC starts to drop).

When the interrupt circuit 104 detects driving of the voltage drop warning line 202, it interrupts the microprocessor 103.

When the microprocessor 103 detects this interrupt, it determines whether a write operation is in progress (step 601), and ignores this interrupt if it is not in operation or a read operation is in progress. If the write operation is in progress, the device control circuit 107
Clear step 6o2), DMA control circuit 101
to the evacuation mode (step 603),
DMA? ! The II control circuit 101 is in the write operation (
(during DMA transfer) is connected to the device control circuit 107 and F I F
0(2) 111, but when the save mode is sent, the device control circuit 107
Stops data transfer to FIFO (21111) and transfers data only to FIFO (21111).

When the data transfer is completed (count value is 0") (step 6o5), the DMA control circuit 101 notifies the microprocessor 103. When the microprocessor 103 receives this notification, DKI
J3 unit number, cylinder number, track number, sector number, cylinder number, trunk number, sector number at the start of operation, the v bit indicating that saved data is stored in PIF (] 21111, and the power-off F I the data storage instruction flag indicating that this has occurred.
It is stored in F 0 (1) 110 (step 606).

The power supply monitoring circuit 105 constantly monitors the power supply voltage +5VDC, and as shown in FIG.
When the value becomes less than C (variable by changing the values of resistors R5 and R6), the emergency interrupt line 201 is driven and an interrupt is issued to the microprocessor 103 via the interrupt circuit 104 (step 604). When the microprocessor 103 receives this interrupt, it determines whether the data transfer to the Flrot 21111 has been completed, that is, whether the DMA control circuit 101
Check whether the evacuation operation has been completed (step 605), and if it has not been completed, set the V bit to "0" and write the information at the time of power failure as shown in Figure 4 to P.
Store in IFO (11110) (step 606).

The battery circuit 112 has a power supply voltage of +5VDC of +4.5
Below VDC (variable by changing resistors R1 and R2), transistor T1 turns off and the voltage from backup battery B becomes FI F 0fLl 11
0 and FIFO (21111), so P
I F 0 (11110 and P I F 0f211
The contents of 14 are retained. When the power is restored, the transistor T1 of the battery circuit 112 is turned on, and the PIF(]1
1110 and P I F 0f211112, the supply of voltage +5VDC is restarted.

When the power is restored, the DKC 2 performs a self-diagnosis (step 608), and then checks F IF (] 11110 (step 609).

Next, the voltage drop instruction flag and the v bit are determined (steps 610 and 611), and if the voltage drop instruction flag is "1" and the V bit is 1, F I F 0 (
FIFO (2) in the sector indicated by the contents of 11110
The data stored in 111 is written and the file is restored (step 612). After this write operation is completed, P IF 0f11110 is cleared and commands from the CPU can be accepted. If the voltage drop instruction flag is “1” and the V bit capacity is 0, then FI
F 0 (11110(7)) Transfers the contents to the RAM 108 and edits the interrupt status to the CPUI (step 613).

When the first command after power restoration is received from the CPU (step 614), it is determined whether there is a power-off status (
Step 615), if there is a power down status, then
Generates an interrupt to the PUI and transfers the contents of FIFO (11110) to the CPUI.The CPUI retains this contents.
Read commands to the destroyed sector are prohibited until the contents of the sector are restored. If there is no power-off status, the steps from step 616 described above are executed.

When the write/read operation in step 618 ends normally (step 619), the completion status is then edited and stored in the RAM 108 (step 620), and the CPU
An interrupt is made to I to notify normal completion.

〔Effect of the invention〕

As explained above, the present invention allows the DKC to automatically restore sectors whose data has been destroyed due to a momentary power outage or power outage without any software intervention after the power is restored, allowing the system to be restarted in a short time. It has the effect of

In addition, even in the worst case where data cannot be saved to the FIF ( ) 21, the CPU can be notified of data-destroyed sectors after power is restored, making it possible to avoid system failures caused by inconsistencies caused by incomplete file updates. be.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
FIG. 3 is a circuit diagram showing the power supply monitoring circuit shown in FIG. 1 in more detail; FIG. 4 is a circuit diagram showing the power supply monitoring circuit shown in FIG. FIG. 5 is a flowchart showing the operation of the input/output control device shown in FIG. 1; FIG. 6 is a flowchart showing the operation of the input/output control device shown in FIG. 1. Is the time chart, Figure 7, a system? FIG. 3 is a diagram illustrating the relationship between the occurrence of KttA disconnection and write sectors. In the figure, ■...Central processing unit (CPU), 2...Input/output control unit (DKC), 3...Magnetic disk device (DKLI), 4...Electronic FA device (PW)
U), 101...DM A! IIIJ control circuit, 102
... bus control circuit, 103 ... microprocessor, 104 ... interrupt circuit, 105 ... power supply monitoring circuit, 106 ... gate, 107 ... device control circuit, 108 ... RAM. 109...FROM. 110...First FIF0°111...Second FIF0°112...Battery circuit, 201...Emergency interrupt line, 202...Voltage drop warning line.

Claims (1)

[Claims] An input/output control device that controls read and write operations of a magnetic disk device based on commands from a central processing unit, comprising: a voltage monitoring circuit that monitors voltage drops; and a voltage monitoring circuit that operates when the voltage drops. a first FIFO that stores information including a unit number, cylinder number, track number, sector number, voltage drop instruction flag, and data storage validity instruction bit of the magnetic disk device; a second FIFO that can store a predetermined number of bytes of data; An input/output control system comprising: a battery circuit that backs up the first FIFO and the second FIFO with a battery; and an interrupt circuit that enables an interrupt to the microprocessor by driving a voltage drop warning line of a power supply of the system. Device.