JPS6217165B2 - - Google Patents

Info

Publication number
JPS6217165B2
JPS6217165B2 JP1347782A JP1347782A JPS6217165B2 JP S6217165 B2 JPS6217165 B2 JP S6217165B2 JP 1347782 A JP1347782 A JP 1347782A JP 1347782 A JP1347782 A JP 1347782A JP S6217165 B2 JPS6217165 B2 JP S6217165B2
Authority
JP
Japan
Prior art keywords
output
circuit
peak value
sample
sampling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1347782A
Other languages
Japanese (ja)
Other versions
JPS58129305A (en
Inventor
Kazuhisa Kanda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP1347782A priority Critical patent/JPS58129305A/en
Publication of JPS58129305A publication Critical patent/JPS58129305A/en
Publication of JPS6217165B2 publication Critical patent/JPS6217165B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01BMEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B11/00Measuring arrangements characterised by the use of optical techniques
    • G01B11/02Measuring arrangements characterised by the use of optical techniques for measuring length, width or thickness

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Length Measuring Devices By Optical Means (AREA)
  • Automatic Focus Adjustment (AREA)
  • Optical Recording Or Reproduction (AREA)

Description

【発明の詳細な説明】 本発明は光位置検出装置の信号処理装置に関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal processing device for an optical position detection device.

2分割検知器を使用した光位置検出装置として
従来一般に使用されている一例の系統図を第1図
に、その波形図を第2図に示す。その動作を以下
説明する。検知器1にパルス光2が入ると、光に
よる電流I1,I2がそれぞれのプリアンプ3,4に
入力され(ここでI1側を+系、I2側を−系とす
る)、その出力E1,E2は、それぞれ増幅器5,6
で増幅される。さらに、入力光の強さに対するダ
イナミツクレンジを得るため対数増幅回路7,8
にこれを加え出力E3,E4を得る。次にパルスの
ピーク値に比例した直流電圧を得るためにまず、
ピーク検出回路9,10でパルス幅を広げ
(E5,E6)、サンプルホールド回路11,12に
より直流電圧E7,E8を得る。このときのサンプ
ルホルド回路のゲート信号は各対数増幅回路の出
力E3,E4を加算器13で加算し、単安定マルチ
バイブレータ14で波形成形した出力E9を使
う。サンプルホールド回路の出力E7,E8の差を
減算器15で、得る。その出力E10はE10=K
(E7−E8)となりE10が、光の位置でKは光の位置
に対する利得定数で、減算器の利得で決まる。こ
こで増幅器3,4.対数増幅回路7,8とピーク
レベル検出回路9,10をそれぞれの系の信号増
幅部という。
FIG. 1 shows a system diagram of an example of a conventional optical position detection device using a two-part detector, and FIG. 2 shows its waveform diagram. The operation will be explained below. When the pulsed light 2 enters the detector 1, the currents I 1 and I 2 due to the light are input to the respective preamplifiers 3 and 4 (here, the I 1 side is the + system and the I 2 side is the - system), and their Outputs E 1 and E 2 are output from amplifiers 5 and 6, respectively.
is amplified. Furthermore, logarithmic amplifier circuits 7 and 8 are used to obtain a dynamic range for the intensity of input light.
Add this to obtain the outputs E 3 and E 4 . Next, in order to obtain a DC voltage proportional to the peak value of the pulse, first,
Peak detection circuits 9 and 10 widen the pulse width (E 5 and E 6 ), and sample and hold circuits 11 and 12 obtain DC voltages E 7 and E 8 . The gate signal of the sample-and-hold circuit at this time is the output E 9 obtained by adding the outputs E 3 and E 4 of each logarithmic amplifier circuit in an adder 13 and waveform-shaping the output E 9 in a monostable multivibrator 14 . A subtracter 15 obtains the difference between the outputs E 7 and E 8 of the sample and hold circuit. Its output E 10 is E 10 = K
(E 7 −E 8 ), where E 10 is the position of the light and K is a gain constant for the position of the light, which is determined by the gain of the subtractor. Here, amplifiers 3, 4 . The logarithmic amplifier circuits 7 and 8 and the peak level detection circuits 9 and 10 are called signal amplification sections of the respective systems.

この信号処理装置において光が検知器の中心に
あり光の強さPのみが変化したとして第2図と第
3図のA,B,Cの3点について考えると、A点
での入力レベルでは系の利得G1と、−系の利得G2
とが一致しているので角度出力E10は0である。
一方、B点ではG1>G2であるため角度出力E0
誤差出力EBを生ずる。同様にC点ではG1<G2
あるため誤差出力ECを生ずる。このように従来
装置では2系統の信号増幅部の利得が全ての入力
光の強さの範囲で一致していないと光が検知器の
中心にあるにもかかわらず、角度誤差出力を生じ
てしまう。
In this signal processing device, assuming that the light is at the center of the detector and only the intensity P of the light changes, considering the three points A, B, and C in Figures 2 and 3, the input level at point A is System gain G 1 and -system gain G 2
Since they match, the angular output E10 is 0.
On the other hand, since G 1 >G 2 at point B, the angle output E 0 produces an error output E B. Similarly, since G 1 <G 2 at point C, an error output E C is generated. In this way, in conventional devices, if the gains of the two signal amplification sections do not match over the entire input light intensity range, an angular error output will occur even though the light is at the center of the detector. .

本発明の目的は光位置検出装置の信号処理装置
において信号増幅部の利得の不一致による角度検
出誤差をなくす装置を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a signal processing device for an optical position detection device that eliminates angle detection errors due to mismatched gains of signal amplification sections.

光位置検出装置の信号処理装置において、2系
統とも同じ信号増幅部を使用することにより信号
増幅部の利得の不一致による角度検出誤差をなく
する装置。
In a signal processing device for an optical position detection device, the device uses the same signal amplification section for both systems to eliminate angle detection errors due to mismatched gains of the signal amplification sections.

以下、本発明の一実施例を図面を参照して説明
する。
Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

本発明の一実施例のブロツク図を第4図に、そ
の波形図を第5図に示す。光が中心にあり入力光
の強さが変化した場合について説明する。
A block diagram of one embodiment of the present invention is shown in FIG. 4, and a waveform diagram thereof is shown in FIG. A case where the light is at the center and the intensity of the input light changes will be explained.

検知器16にパルス光17が入射することによ
り生ずる光電流I3,I4がそれぞれのプリアンプ1
8,19で増幅され、その出力をE11,E12とす
る。−系の出力E12のみ遅延回路20を通し、時間
Tだけ遅延させてE13とする。E11とE13とを加算
器21で加算し(E14)、更に対数増幅回路22お
よびピーク値検出回路23を経て出力E15を得
る。E15を+系のサンプルホールド回路24と−
系のサンプルホールド回路25に同時に加える。
そのときの+系サンプルホールド回路24のゲー
ト信号E16はプリアンプ18の出力を単安定マル
チバイブレータ26により波形整形したものを使
い、−系サンプルホールド回路25のゲート信号
E17は遅延回路出力E13を単安定マルチバイブレー
タ27で波形整形したものを使う。それぞれのサ
ンプルホールド回路出力E18,E19を減算器28に
加え差出力E20とする。このE20をサンプルホール
ド回路29に加えて角度出力E22を得る。サンプ
ルホールド回路29のゲート信号はE17をさらに
単安定マルチバイブレータ30に加え波形整形し
たE21を使う。以上の説明では、第1図に示す増
幅器5,6は図示されていないが、これはその影
響が少ないためで、第4図ではプリアンプ18,
19にそれぞれ含めている。その代りに別に加算
器21の直後に1個の増幅器を設けても良い。こ
のように本発明は信号増幅部を+系と−系で共用
しているために、従来のように利得の不一致によ
る角度誤差出力がなくなる。
Photocurrents I 3 and I 4 generated when the pulsed light 17 is incident on the detector 16 are transmitted to the respective preamplifiers 1
8 and 19, and their outputs are designated as E 11 and E 12 . - Only the output E 12 of the system is passed through the delay circuit 20 and delayed by a time T to become E 13 . E 11 and E 13 are added by an adder 21 (E 14 ), and further passed through a logarithmic amplifier circuit 22 and a peak value detection circuit 23 to obtain an output E 15 . Connect E 15 to + system sample hold circuit 24 and -
It is simultaneously added to the sample hold circuit 25 of the system.
At that time, the gate signal E 16 of the + system sample and hold circuit 24 is the output of the preamplifier 18 whose waveform is shaped by the monostable multivibrator 26, and the gate signal of the - system sample and hold circuit 25 is used.
E 17 uses the delay circuit output E 13 whose waveform has been shaped by a monostable multivibrator 27. The respective sample and hold circuit outputs E 18 and E 19 are added to a subtracter 28 to obtain a difference output E 20 . This E 20 is applied to a sample and hold circuit 29 to obtain an angular output E 22 . The gate signal of the sample and hold circuit 29 uses E 21 obtained by adding E 17 to a monostable multivibrator 30 and shaping the waveform. In the above explanation, the amplifiers 5 and 6 shown in FIG. 1 are not shown, but this is because their influence is small, and in FIG.
19 respectively. Alternatively, one amplifier may be separately provided immediately after the adder 21. As described above, in the present invention, since the signal amplification section is shared by the + system and the - system, there is no angular error output due to gain mismatch, which is conventional.

本発明は以上説明したように、信号増幅部を+
系、−系で共用することにより、入力光の強さの
変化による角度誤差出力はなくなる。さらに回路
調整は2系統を一致させる必要がなくなるので調
整が容易になる。
As explained above, the present invention provides a signal amplification section with +
By sharing it with the system and - system, there will be no angular error output due to changes in the intensity of input light. Further, since it is no longer necessary to match the two systems in circuit adjustment, the adjustment becomes easier.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図と第2図は従来の信号処理装置のブロツ
ク図とその波形図、第3図は+系、−系の信号増
幅部で利得の不一致を生じた場合の各系の直流電
圧出力と角度出力の関係を示す図、第4図は本発
明の信号処理装置のブロツク図、第5図は第4図
の波形図を示す図である。 1,16……検知器、2,17……光、3〜
6,18,19……増幅器、7,8,22……対
数増幅器、9,10,23……ピーク値検出回
路、11,12,24,25,29……サンプル
ホールド回路、13,21……加算器、15,2
8……減算器、20……遅延回路。
Figures 1 and 2 are a block diagram of a conventional signal processing device and its waveform diagram, and Figure 3 shows the DC voltage output of each system when a gain mismatch occurs in the + and - system signal amplification sections. FIG. 4 is a block diagram of the signal processing device of the present invention, and FIG. 5 is a diagram showing the waveform diagram of FIG. 4. 1,16...Detector, 2,17...Light, 3~
6, 18, 19... Amplifier, 7, 8, 22... Logarithmic amplifier, 9, 10, 23... Peak value detection circuit, 11, 12, 24, 25, 29... Sample hold circuit, 13, 21... ...adder, 15,2
8...Subtractor, 20...Delay circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 2個に分割された光検知器の各分割部からの
光電流のうち、一方を所定時間遅延させる遅延回
路と、この遅延回路の出力と他方の光電流とを加
算する加算器と、この加算された出力を増幅する
増幅器と、この増幅器の出力のピーク値を検出す
るピーク値検出回路と、このピーク値を前記所定
時間間隔のサンプリングパルスでサンプルホール
ドする2つのサンプリング回路と、この2つのサ
ンプリング回路出力の差をとる減算器と、この減
算器出力を前記時間遅延を受けたサンプリングパ
ルスと同期したパルスでサンプリングする回路と
を備えて成ることを特徴とする光位置検出装置。
1. A delay circuit that delays one of the photocurrents from each of the two divided parts of the photodetector by a predetermined time, an adder that adds the output of this delay circuit and the other photocurrent, and an amplifier that amplifies the added output, a peak value detection circuit that detects the peak value of the output of this amplifier, two sampling circuits that sample and hold this peak value with sampling pulses at the predetermined time intervals; 1. An optical position detection device comprising: a subtracter that takes the difference between sampling circuit outputs; and a circuit that samples the subtracter output with a pulse synchronized with the time-delayed sampling pulse.
JP1347782A 1982-01-29 1982-01-29 Optical position detecting device Granted JPS58129305A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1347782A JPS58129305A (en) 1982-01-29 1982-01-29 Optical position detecting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1347782A JPS58129305A (en) 1982-01-29 1982-01-29 Optical position detecting device

Publications (2)

Publication Number Publication Date
JPS58129305A JPS58129305A (en) 1983-08-02
JPS6217165B2 true JPS6217165B2 (en) 1987-04-16

Family

ID=11834199

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1347782A Granted JPS58129305A (en) 1982-01-29 1982-01-29 Optical position detecting device

Country Status (1)

Country Link
JP (1) JPS58129305A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20240076408A (en) * 2019-09-02 2024-05-30 삼성전기주식회사 Printed circuit board

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2658043B2 (en) * 1987-04-15 1997-09-30 松下電器産業株式会社 Loop / gain controller
JPH03226624A (en) * 1990-01-31 1991-10-07 Nec Corp Star scanner
JP3887480B2 (en) * 1998-03-20 2007-02-28 パイオニア株式会社 Pre-pit detection device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20240076408A (en) * 2019-09-02 2024-05-30 삼성전기주식회사 Printed circuit board

Also Published As

Publication number Publication date
JPS58129305A (en) 1983-08-02

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