JPS62172829A - Frame synchronizing system - Google Patents

Abstract

PURPOSE:To execute frame synchronization which is scarcely influenced by a noise, by bringing a one frame portion of a signal of a frequency of 1/n, to a high speed Fourier transform processing and averaging it, when detecting a phase of a signal of a frequency of 1/n of a sampling frequency. CONSTITUTION:A phase detection of a signal f3 wave of a frequency of 1/n of a sampling frequency, for deriving a decoding start time point is executed by a phase conversion by bringing a one frame portion of a signal of a frequency of the 1/n concerned, to a high speed Fourier transform processing and averaging it, and a frame synchronization error is corrected. That is to say, by averaging the signal of the frequency of 1/n of the sampling frequency in one frame by a high speed Fourier transformer FFT 8, an average phase in one frame is derived, and by this phase, a timing error of an encoding start and a decoding start is corrected so as to become less than one sample. Accordingly, even if several sample points are masked by a noise, this influence is averaged, and a frame synchronization which is scarcely influenced by a noise is executed.

Description

[Detailed Description of the Invention] [Summary] In a frame synchronization method for encryption and decoding of a frequency scramble encryption method for audio signals, phase detection of a signal having a frequency of 1/n of the sampling frequency is performed using the frequency of the 1/n. Phase detection is performed by fast Fourier transform processing and averaging of one frame of the signal, and by correcting frame synchronization errors, frame synchronization can be achieved accurately even in the presence of noise. It is.

[Industrial application field]

The present invention relates to an improvement in a frame synchronization method for encrypting and decoding a frequency scrambling encryption method, which is used as a countermeasure against secrecy of voice signals in a voice band communication channel.

Frequency scrambling encryption is often used as a measure to prevent confidential communication of voice signals in voice band communication channels, as it is a method that expands the band and reduces signal delay.

An example of this method will be described below.

Figure 4 is a block diagram of the frequency scrambling encryption method.
Figure 5 is a waveform diagram of each part of Figure 4, and (A) to (D) are waveform diagrams of each part of Figure 4.
This corresponds to points a'' and d in the figure.

In the figure, 1 and 7 are A-D converters, 2.8 is a fast Fourier transformer (hereinafter referred to as FFT), 3 is a spectrum insertion unit, 4 is an encryption device, and 5.11 is an inverse fast Fourier transformer (hereinafter referred to as FFT). 6.12 is a DA converter, 9 is a spectrum remover, 10 is a decoding device, and 13.14 is a synchronization circuit.

The audio signal shown in FIG. 5(A) is sampled by an A-D converter at a sampling frequency of 8 KHz, with 32 m5 as one frame, based on confidential communication strength, delay, processing capacity, etc., and converted into a digital signal. It is processed by FFTz2 and converted into the frequency axis, and a dummy spectrum is inserted in the spectrum insertion unit 3 to flatten the envelope of the secret signal, resulting in a signal with the frequency sequence shown in Fig. 5 (B). input into the encoding device 4, scrambled (transposed) with a key,
The signal becomes the signal shown in FIG.
) is converted into a flat analog signal and output to the receiving side as a secret message (number i).

On the receiving side, it is converted into a digital signal by an A-D converter 7, converted into a frequency sequence spectrum by FFT 8,
The dummy spectrum is removed by the spectrum remover 9,
Descrambling using a key in the decryption device IO (reverse device)
The audio signal is converted into a time waveform by inverse FFTII and decoded by the DA converter 12, thereby obtaining an audio signal.

In this case, at the start of encrypted communication, a signal for synchronization is sent from the synchronization circuit 13 in order to synchronize encryption and decryption.
The synchronization circuit 14 on the receiving side matches the start point of encryption with the start point of decryption, but it is desirable that this frame synchronization can be achieved accurately even in the presence of noise.

[Conventional technology]

Figure 6 is a block diagram of a conventional frame synchronization method;
The figure is an explanatory diagram of frame synchronization using the fl and f2.2 waves in Figure 6. Figure 8 is a characteristic diagram of the delay amount with respect to the amplitude ratio of the fl and f2.2 waves. Figure 9 is a sampling frequency (8K
FIG. 10 is a characteristic diagram showing the phase shift when the frequency of 1/n of H2) is 2 KHz, and FIG. 10 is a diagram showing the amplitude in the case of 0 to 3 sample synchronization shifts at each sample time point in FIG.

In the figure, 15 is a clock generator, 16.23 is a counter, 1
7 is a signal generation section, 18 is a FL wave detection section, 19.21 is an arithmetic circuit, 20 is a shift circuit, and 22 is an amplitude detection circuit, and the same reference numerals indicate the same functions throughout the drawings.

A clock pulse generated by the clock generator 15 causes a counter 16 to generate a frame pulse and an encryption start pulse.

Two waves fl and f2 of different frequencies are alternately input from the signal generator 17 to the inverse FFT 5 (used for encryption processing and synchronization processing) in synchronization with the frame pulse, as shown in FIG. 7(A).
As shown in the figure, the delay is received on the receiving side as a sine wave on the time axis alternately for each frame, and the number of frames that can be corrected within (n-1) sampling, for example, 20 frames, is received via the D-A converter 6. send to the side. Next, a signal with a frequency of 1/n of the sampling frequency, for example, if the sampling frequency is 8KHz, a signal r3 of 2KHz, which is 1/4, is sent out from the signal generator 17, and is processed by inverse FFT5 as a sine wave on the time axis for one frame. Above predetermined frame D-A converter 6
Send via.

On the receiving side, the f1 wave detector 18 detects the first fl wave of the signal shown in FIG.
(shared for synchronization processing and decoding processing) sends a start signal.

In FFT8, from this point on, from one frame's worth of signals (including f2 wave due to delay), <fl, f2. The spectrum amplitude of the wave is extracted and sent to the arithmetic circuit 1'l.

Arithmetic circuit 1. 'l is the difference in the number of digits when the amplitude al of the fl wave and the amplitude a2 of the f2 wave are expressed in binary numbers, 1ogz (a
Find a value approximated to l/a2) and calculate logz (
Using a synchronization table created according to a characteristic diagram showing the relationship between al/a2) and the delay amount Δτ, the synchronization deviation is estimated and sent to the shift circuit 20, which calculates the shift amount ΔS up to two frames later, That is, a pulse indicating the start of the frame is sent to the FFT 8 and the counter 23, and as shown in FIG. 7(C) (b), [1, f2 .
The operation of extracting the spectrum amplitude of the wave, estimating the synchronization shift in the arithmetic circuit 19, and sending a pulse informing the shift amount up to two frames later, that is, the start of the frame, to the FFT 8 and the counter 23 is repeated for 20 frames.

In this way, the timing error will be within (n-1)=3 samplings.

When the counter 23 counts 20 frames, it sends a switching signal to the shift circuit 20 and inputs it to the arithmetic circuit 21.
Switch to the side.

At this time, the 2KHz f3 wave shown in FIG. 9 is detected by the amplitude detection circuit 2.
Enter 2.

This input 2KHz signal is adjusted to the correct synchronization position (10th
If the reception shifts at sample point O) in the figure, the phase shift is 0 and 1
90 degrees if a sample is off, 18 degrees if 2 samples are off.
If there is a shift of 0 degrees and 3 samples, it becomes 270 degrees.

As shown in FIG. 10(A), the amplitude of this 2 KHz signal when the correct synchronization position sample point O and the point shifted by 1 to 3 samples is shown as shown in FIG. 10(B).

The amplitude data shown in (B) is stored in the arithmetic circuit 21 in the form of a table containing data at two points, for example, the data at the O sample point and the 3 sample point. is detected and sent to the arithmetic circuit 21, where it is compared with a table to determine the timing error, and the shift it is sent from the shift circuit 20 to the amplitude detection circuit 22.
If the data is sent to the counter 23 and the timing of the sample point is corrected for a predetermined number of frames, for example, one frame, the timing error from the start of encryption will be within one sample.

At this point, the counter 23 issues a decoding start pulse.

In this way, fl, f2. Due to the wave, on the arithmetic circuit 19 side,
The timing error between the start of encryption and the start of decryption is (n-1
), and the f3 wave is used to reduce the timing error to within one sample on the arithmetic circuit 21 side.

[Problem that the invention seeks to solve]

However, in order to reduce the timing error to within one sample using the f3 wave, it is necessary to look-amplify the daple using the instantaneous amplitude values at two sampling points of the three waves, and calculate the phase shift (sample shift) from the correct frame position. Since this is carried out by detecting the two points, there is a problem that if the amplitudes at these two points vary due to noise, the phase detection may be incorrect.

[Means for solving problems]

The above problem is that phase detection of the signal f3 wave with a frequency of 1/n of the sampling frequency in order to find the decoding start point requires fast Fourier transform processing of one frame of the signal with a frequency of 1/n. This problem is solved by the frame synchronization method of the present invention, which performs phase detection by averaging and corrects frame synchronization errors.

[Effect]

According to the present invention, the average phase within one frame is obtained by averaging signals with a frequency of 1/n of the sampling frequency within one frame using FFT, and encryption is started using this phase in the same manner as before. The timing error between the start of decoding and the start of decoding is corrected to within one sample.

Therefore, even if several sample points are masked by noise, the shadows are averaged out, so frame synchronization can be performed with less influence of noise ξ.

〔Example〕

Fig. 1 is a block diagram of a frame synchronization circuit on the receiving side according to an embodiment of the present invention, and Fig. 2 shows the f3 wave at 1 of the sampling frequency.
/4 is an explanatory diagram of the phase shift determination operation of the arithmetic circuit of FIG. 1 in the case of 4, and FIG. 3 is an explanatory diagram of the operation of the arithmetic circuit of FIG. 1 in a general case.

In the figure, 24 is an arithmetic circuit, 25.26 is a sign determination unit, 27 is a comparison circuit, 28.31 is a phase determination unit, and 29 is Cos −
'a3r/8 calculation, 30 indicates a 5in-'a3i/A calculation section, and 32 indicates a phase determination table section.

The difference between FIG. 1 and FIG. 6 is that the amplitude detection circuit 22 is not used for phase detection using 13 signal waves having a frequency of l/H of the sampling frequency, but an FFT 8 is used.

To explain this point, Fig. 9 and 10 with n=4
When the 2KHz f3 wave shown in the figure is subjected to Fourier transform processing for one frame using FFT8, the amplitudes of the real part a3r and the imaginary part a3i of the frequency are as shown in Fig. 2 (B), and the real part is 0 in Fig. 10. At the sample time, the imaginary part is the same as at the 3rd sample time, and the difference between the absolute values of the real part a3r and the imaginary part a3i, and A/2. If the sign is determined using a threshold value of -A/2, the result will be as shown in FIG. 2(C).

Therefore, as shown in FIG. 2(A), the arithmetic circuit 24
The signs of the real part a3r and the imaginary part a31 of the output of T8 are determined by the sign determining parts 25 and 26, and the difference in absolute value between the real part a3r and the imaginary part a3i is determined by the comparator circuit 27 and the phase determining part 28, it can be determined whether there is a deviation or a deviation of 1 to 3 samples. If the shift circuit 20 shifts the timing according to this deviation, the timing error can be kept within 1 sample as in the conventional case. .

When n takes a value other than 4, as shown in Figure 3,
From the real part a3r and imaginary part a3i of the output, Co5-
'a3r/A calculation section 29.5in-'a3i/A calculation section 30, where A=(aπT blue 3iT Cos 'a3r/A and 5in-'a3i/A are calculated, inputted to phase determination section 31, and If the phase is determined using the phase determination table unit 32 which has a table prepared in advance that can determine the phase from data such as You can.

In the above case, the output of FFT8 is the average phase within one frame obtained by averaging the 18th frequency of 1/n of the sampling frequency within l frame, so several sample points are masked by noise. However, since this influence is averaged out, frame synchronization can be performed with less influence of noise.

Incidentally, since the FFT 8 is used in common, the circuit scale can be reduced.

〔Effect of the invention〕

As explained in detail above, according to the present invention, there is an effect that frame synchronization between the start of encryption and the start of decryption can be performed with less influence of noise.

[Brief explanation of drawings]

Figure 1 is a block diagram of a frame synchronization circuit on the receiving side according to an embodiment of the present invention. Figure 2 is an explanation of the phase shift determination operation of the arithmetic circuit in Figure 1 when the f3 wave is set to 1/4 of the sampling frequency. Figure 3 is an explanatory diagram of the operation of the arithmetic circuit in Figure 1 in a general case; Figure 4 is a block diagram of the frequency scramble encryption method; Figure 5 is a waveform diagram of each part in Figure 4; The figure is a block diagram of a conventional frame synchronization method. Figure 7 is an explanatory diagram of frame synchronization using fl, f2, and 2 waves in Figure 6. Figure 8 is the amount of delay versus the amplitude ratio of fl, f2, and 2 waves. Figure 9 is a characteristic diagram showing the phase shift when the frequency of 1/n of the sampling frequency (8KH2) is 2 kHz, Figure 10 is the characteristic diagram of O ~ at each sample time in Figure 9.
It is a figure which shows the amplitude in the case of 3-sample same-friend synchronization. In the figure, 1.7 is an A-D converter, 2.8 is a fast Fourier transformer, 3 is a spectrum inserter, 4 is an encryption device, 5.11 is an inverse fast Fourier transformer, 6.12 is a D- A converter, 9 is a spectrum remover, 10 is a decoding device, 13.14 is a synchronization circuit, 15 is a clock generator, 16.23 is a counter, 17 is a signal generation section, 18 is an FL wave detection section, 19. 21.24 is an arithmetic circuit, 20 is a shift circuit, 22 is an amplitude detection circuit, 25.26 is a sign determination unit, 27 is a comparison circuit, 28.31 is a phase determination unit, 29 is a Co51a3r/8 arithmetic unit, 30 is a 5in -1a3i/8 calculation unit 32 indicates a phase determination table unit. , Kizen Kazumi's Shogun Village Ikull's e1L However, 1's 7th Shiichimu fellow ■ Giant Pilgrimage's Blind Tsukuen #1 Country

Claims (1)

[Claims] After alternately transmitting two waves with different frequencies in a predetermined frame,
A signal with a frequency of 1/n of the sampling frequency (n is an integer of 3 or more) is transmitted for one or more predetermined frames, and after detecting the first transmitted wave on the receiving side, fast Fourier transform processing is performed to determine the corresponding period of one frame. The synchronization error is determined by the spectrum amplitude of the two waves, and after iteratively corrects this synchronization error to be within (n-1) sampling periods, the phase of a frequency of 1/n of the sampling frequency is detected and the frame synchronization error is corrected. , In the frame synchronization method for encryption and decoding of the frequency scrambling encryption method for audio signals, the phase detection of the signal with a frequency of 1/n of the sampling frequency is carried out at high speed for one frame of the signal with a frequency of 1/n of the sampling frequency. A frame synchronization method that corrects frame synchronization errors by performing phase detection using Fourier transform processing and averaging.