JPS6217801A - Automatic correcting circuit for residual error - Google Patents

Abstract

PURPOSE:To remove a servo error by storing the size of a phase error, determining a correcting variable and the direction of a residual error and automatically adjusting a phase locking position. CONSTITUTION:In an automatic residual error correcting circuit for a servo circuit, a correcting variable is determined on the basis of the contents of a phase detecting counter 120 at the input of a reference signal S (at the end of a phase detecting time) and stored in a moving variable counter 145. The direction of a residual error is transferred to a moving direction flip-flop (FF) 146, and at a time T1, the moving variable is added/subtracted by a correcting counter 147. At a time T2, the counted result (phase information) of the counter 120 is added/subtracted to/from the contents (residual error information) of the counter 147 to obtain feedback information MFD to be fed back to a speed loop. Even if the locking position is shifted due to the change of a load or the like, the shift can be turned to zero without fail and operation expanding DC gain to an infinite level can be expected at the time of sudden phase shift.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention automatically corrects so-called residual errors that remain uncontrollable due to the finite DC gain of the servo circuit of a VTR, especially the servo circuit, without manual adjustment, and eliminates servo errors. This is related to improvements to eliminate this problem.

Conventional servo circuits, for example, in the drum drive servo circuit of a VTR, the purpose of the phase servo circuit is to maintain a constant phase between the output signal of the pulse generator attached to the drum and the reference signal. The residual error will remain as a phase error. This phase error, together with other phase errors, such as pulse generator installation errors, mechanical variations between VTRs, and servo circuit component variations, is caused by the video head switching position standard (VSYNC). Previous 7H±1・
If it falls within 5I-I), there is no need for adjustment, but manual adjustment is usually done to correct all variations. Another problem is the influence of residual errors due to temperature changes. When the temperature drops to around 0°C, the oil in the motor bearings becomes hard, increasing the load on the motor. This results in a lack of motor torque, which changes the position of the phase lock and causes the servo to be applied. This results in a phase error. Generally, this phase shift is on the order of tens of Hz, so a temperature compensation circuit is used to keep the phase error to a minimum, but there are limits to the selection of components, and operation at low temperatures is a major problem. This can also be said to be a residual error caused by temperature changes.

Due to the shift in the lock phase, switching points appear on the screen, and skew becomes visible, making defects visually obvious.

The present invention has been made to improve the drawbacks of the prior art, and detects the residual error of the servo circuit, determines the amount of correction and the direction of correction according to the detected amount of error, and integrates the amount of correction. , is held, and an error voltage corresponding to the correction amount and correction direction is applied to the servo circuit until the residual error becomes zero.

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a digital servo circuit to which the present invention is applied will be described below with reference to the drawings.

In general, the most commonly used circuit system for equipment that requires servo control for a drive motor (for example, a VTR) generates a ramp voltage from a reference signal (or controlled signal), and generates a ramp voltage from the controlled signal. (or reference signal), sample and hold the ramp voltage, and use it as the terminal voltage of the motor to be controlled.

FIG. 1 is a block circuit diagram of such a conventional servo system, and 10 is a terminal for receiving a tacho pulse representing the rotation of the motor 12. This tacho pulse, that is, the controlled word PG ( A signal generated from the control image 12,
In the case of a VTR, the signal is obtained from a magnet attached to the rotating head driver 11 and a fixedly placed coil, but it may of course be obtained from a frequency generator FG. ) is waveform-shaped at the waveform-forming port f%14, and then applied to the ``th monomulti 16'' and the second monomulti 1-8.

These Mono Multi 16.18 and Mono Multi 2 described later
8 is provided for the purpose of not restricting the mounting position of the PG coil or magnet, preventing the mounting accuracy from becoming stricter, and correcting residual errors of the servo that cannot be fully controlled. FIG. 2 shows the output waveform of the first monomulti 16, and FIG. 2g shows the output waveform after passing through the second monomulti 18 and the lamp voltage generation circuit 20. Reference numeral 26 in FIG. 1 is a reference signal generation circuit, and this reference signal is necessary to set the controlled object 12 at the correct speed or in a constant rotational phase relationship, and usually consists of a crystal oscillator, line power frequency source, etc. Good too. FIG. 2g shows, for example, a synchronous waveform as this reference signal.

28 is the above-mentioned monomulti, 30 is a sampling pulse generation circuit, and their output waveforms are shown in FIGS. 2g and 2f. A sampling pulse circuit section 32 from the sampling pulse generating circuit 30 samples the ramp section of the ramp voltage generating circuit 20 as shown in FIG. 2g and f. FIG. 2g shows the motor voltage when the sampled voltage is applied to the motor 12 via the hold circuit 22 and the motor drive amplifier 24. A differential voltage level 8E between applied voltages E□ and E2 indicates a servo error voltage.

In contrast to the servo system that samples the lamp voltage and generates an error, there is a digital error detector. Several methods can be considered for configuring this digital error detector, and some are already known.

The principle of this digital error detector will be explained below with reference to the timing chart of FIG.
Since the purpose of the servo is to keep the time interval (period 1'' in Figure 3 g) between the G signal (Figure 3 g) and the V synchronization signal which is the reference signal at a certain constant value, in the digital type counts this time interval T with a sufficiently fast clock, and determines whether it is smaller or larger than the target number based on the count result.
A counter clock is generated as shown in Fig. g, and a counter consisting of N bits counts the number of clocks. In FIG. 3, e indicates the output of the first bit of the counter (that is, the output of the least significant bit) cT2t, and g indicates the output CTN of the Nth bit of the counter. At the end of 1'' in Figure 3g, that is, when the ■ synchronization edge has arrived, the most significant bit CTN of the counter should be in one of the states ■, ■, and ■, as shown in Figure 3g. , ■ means the interval between T is too wide, ■ means the optimal interval, ■ means T
Indicates that the spacing is too narrow. This is the desired time interval T
Just when it reached , the counter went through one cycle and all 710 IT
This is the result of selecting the clock frequency or the number of counter stages so that . Therefore, in the analog system related to FIGS. 1 and 2, the servo error is directly obtained as a voltage value, but in the digital system, the servo error is given as a digital value as a counter value. Therefore, the servo error given as a digital value needs to be converted into an analog voltage in some manner before being given to the motor.

Methods of converting into such an analog voltage include a method using a DA converter and a method using PWM (pulse width modulation). In the latter method, when sampling the center of the lamp voltage using the analog method described above, that is, PG and V
When the synchronization phase relationship is optimal, PWM (7) “i”
and II OIT (7) Ratio or duty of 50:5
The voltage is set to 0, that is, 1, and is designed to have the same value as the analog system after being converted to a DC voltage through a filter.

Then, due to the error obtained from the digital value, this PWM
“1”.

By varying the ratio of 0", it is possible to perform a function completely equivalent to that of an analog method. At this time, the PWM repetition period is set by adjusting the phase delay caused by the filter for converting to DC voltage to the frequency at which the error occurs. It must be chosen to have a negligible value.

Since a servo circuit consisting of such a PWM type digital error detector can basically be realized entirely using logic circuits, 1) highly accurate control can be achieved;

2) Adjustments due to variations in parts can be avoided.

3) No change in temperature or over time.

4) High integration is possible.

However, on the other hand, a quantization error due to the clock frequency always occurs, and as a result, it becomes an error element for the servo, so the design must be such that it does not affect the servo.

A servo circuit having a digital error detector that satisfies such requirements, particularly a servo circuit which is the subject of the present invention and has been improved for use with a rotary head drum servo of a VTR, will be described below. Explain the original role.

When constructing a drum servo for a VTR using a DC motor, the focus is on a phase servo that sets the position of the video head of the drum in a constant phase relationship with a specific reference signal. Furthermore, as a matter of course, in order for the phases to match, the speeds must match, and at the same time, a speed servo is also required.

In other words, in a VTR, the velocity servo loop can be considered to play a necessary role in applying phase servo. It also has the role of damping, which controls the speed so that it does not deviate greatly from the speed change from the phase servo loop when locking the phase, and speeds up the pull-in. This speed loop is not necessary when using an AC motor that can basically be expected to have constant speed. FIG. 4 shows a timing chart of this phase servo.

Fig. 4a shows the PG indicating the position of the video head, and Fig. 4 shows the reference signal, for example, the recording signal V same period signal, the reproduction CTL synchronization signal, the 30Hz crystal frequency source, etc. There may be. Phase servo is PG
The phase φ of the double signal and the reference signal is maintained at a constant phase.

Of course, the reference signal at this time differs depending on the recording/playback mode of the VTR, and also changes depending on whether tracking is performed using a drum or capstan feed. However, the principle of keeping the phase φ constant in FIG. 4 remains the same.

Figures 5 and 6 show a VT constructed according to the principles described above.
These are circuit diagrams of the R drum servo, in particular, FIG. 5 shows the speed servo part, and FIG. 6 shows the phase servo part. terminals 50 and 5
The PGA and PGB signals applied to the rotary head drum are two rotational speed tacho pulse information from pickup coils approximately 186 times apart that cooperate with, for example, six pole pieces equally spaced on the rotating head drum. Therefore, the PGA and PGB signals are each 6 per revolution of the rotating head drum.
occurs as individual tacho pulses. The PGA is configured to precede the PGB. The amplified PGA is amplified by each PG doubler signal amplifier 51.53.
The signal is delayed by a predetermined amount by the speed servo delay circuit 54, and is applied to the set input of the flip-flop 56.
The power amplified PCB signal is applied directly to the reset input of flip-flop 56. This delay circuit 54
This is not necessarily necessary as it is used to simplify the counting operation and configuration when counting the time length between the A and PGB signals with a counter and making the counted value correspond to the speed command voltage given to the motor. .

On the other hand, cascaded flip-flops 58 and 60 are provided. A set input of flip-flop 58 receives the amplified PGB signal, and a set input of flip-flop 60 receives the output of flip-flop 58. The output FF of the flip-flop 60 serves as a reset input for these two flip-flops 58 and 60. A timing signal Ti, which will be described later, is applied to the clock input CP of the flip-flop 60 on the output line 6'' of the clock generation counter 62.
2 Given from a.

This counter 62a has, for example, a 3.58 MHz crystal 64 and generates timing clock signals of four different frequencies. The line 62b generates a 3.58 MHz clock ×O, the line 62c generates a clock ×1 with a frequency of *O/4 (895 KHz), and the line 62d generates a clock ×1 with a frequency of *O/32 (112 KHz)*2 occurs.

The clock x0 on the output line 62b is provided as a clock input CP of a counter 66 having, for example, a 10-bit configuration (1024 base). The MSD signal indicating the maximum bit position of the counter or the timing at which the counter returns to 0 is applied as a falling bit to the differentiating circuit 68 as shown in the figure, and then becomes a reset pulse for the flip-flop 70. On the other hand, the timing pulse T on the output line 62a
i becomes the set input of the flip-flop 76. FF2, which is the output of the flip-flop 70, is a PWM output, the period of which is determined by the Ti clock, and the reset pulse, that is, the MSD signal, is the duty ratio of FF2,
The energizing power level to motor 76 is therefore determined.

The PWM output FF2 of the flip-flop 70 is connected to the integrator 72.
The signal is converted into a direct current by the motor drive amplifier 74, and then the power is amplified by the motor drive amplifier 74.

The buffer counter 66 is reset in a manner described below,
The timing of this reset changes the timing of the reset signal of the PWM flip-flop 70, and thus changes the motor energizing power level.

The timing of resetting the buffer counter 66 is determined by the MSD output of the speed detection counter 78. This counter 78 is also 1 like the buffer counter 66 mentioned above.
It may be a 024 decimal counter. This counter 78
is the *1 clock strobed by the FF1 output at the AND gate 82 and the FF at the AND gate 84. ×0 clock strobed by output and AND gate 8
The xl clock strobed by the MFD output from the phase servo section, which will be described later in 6, is received at the clock input CP via an OR gate 88. Also, as a reset signal, the amplified PGA signal is sent from the PGA amplifier to the PGA'
Take it as a signal. The MSD falling output of the counter 78 is differentiated by a differentiating circuit 90, and then an AND gate 80
And FFi. is synchronized with the output and then buffer counter 6
6 as a reset input.

Figure 6 shows the phase servo circuit part, whose output is the MFD.
The signal is applied to the speed circuit section of FIG. 5 as the MFD input of AND gate 86. A terminal 100 is supplied with a tacho pulse PGC representing the rotational phase of the rotary head drum from a pickup coil associated with a pole piece fixed to the rotary head drum, while a terminal 102 is supplied with a reference pulse serving as a phase reference. PGC of terminal 100
The signal is connected to the set input of flip-flop 108 via amplifier 104 and delay circuit 106.

On the other hand, the phase reference pulse at terminal 102 is applied to the reset input. That is, the output of flip-flop 108 indicates the phase difference (including fixed delay) of the rotating head drum relative to the reference phase. This flip-flop output is applied to AND gate 110 as a x2 clock strobe signal.

On the other hand, two cascaded flip-flops 112 and 114 are provided which provide a synchronizing signal FF21 as well as the FF1o output of the speed control loop. The circuit configuration is the same as that of the velocity loop flip-flop 58.60 described above, except that the set input of the first flip-flop 112 receives a phase reference pulse.

The FF21 output of the flip-flop 114 serves as a x0 clock strobe signal in the AND gate 116. The output of AND gates 110 and 116 is OR gate 1
18 as a clock input to a phase error detection counter 120.

This counter 120 is, for example, a 256-decimal counter,
The amplified PGC signal, that is, the output PGC' of the amplifier 104
reset by . The MSD output in the form of a falling edge of the counter 120 is passed through a differentiating circuit 122 to A
It is synchronized with the FF2□ output at the ND gate 124, and then applied to the phase loop buffer counter 126.

The counter 126 is, for example, a 256-decimal counter,
A shift signal T SFT, which will be described later, is applied to the D gate 128.
*1 clock slobed with AND gate 13
The ×O clock strobed with the FF21 signal at 0 is received as a clock input via an OR gate 132. The MSD falling edge of the counter 126 is the differential circuit 1-3.
4 and this output pulse is differentiated by flip-flop 13.
6 reset input. flip flop 13
The set input of 6 receives the PGA' signal and its output provides the MFD signal which is applied to the velocity loop.

The T SFT signal mentioned above is passed through the flip-flop 140, A
This is obtained by a circuit consisting of an ND gate 144, for example a 256-base counter 142. flip flop 140
A PGA' signal is applied to its set input, and a signal indicating that the count value of the counter 14 has reached the 256-decimal count value is applied to its reset input. flip flop 1
The Q output of 40 outputs the T SPT signal and the ζ output provides a signal to reset counter 142. counter 14
2 receives at its clock input a ×1 clock strobed with the T SFT signal.

Figure 7 shows the velocity and phase loops of Figures 5 and 6.
3 is a waveform diagram for explaining the operation of a digital servo consisting of a PGC input terminal 100; FIG.
The signal, (b) is the PGA signal applied to the terminal 50, (c
) is the PGB signal given to terminal 52, (d) is the PGB signal given to terminal 1
02 (for example, a V synchronization signal whose frequency is divided by 1/2). PGC signal is 1 per drum rotation
Therefore, the period between PGC pulses corresponds to the time for one rotation of the drum. Further, there are six PGA and PGB pulses in each drum one rotation period, that is, a PGC pulse.

(e) Figure shows the operating waveform of the phase loop, (e -1)
is the output of the delay circuit 106, rising at the position of the PGC pulse, and falling after a predetermined amount of delay.

(e-2) shows the output waveform of the flip-flop 108. That is, it rises at the falling edge of the delay circuit output (e-1) and falls at the V synchronization signal position (d). (e
-3) shows the output waveform of the flip-flop 112. This rises at the V synchronization signal position, and the timing signal Ti
fall with the arrival of (e-4) shows the waveform of the output FF2□ of the flip-flop 114, which is set at the reset time of the flip-flop 112 and reset when the next Ti timing pulse arrives. Therefore, terminal 100
The phase error associated with the phase difference between the PGC pulse at terminal 102 and the phase reference pulse at terminal 102, i.e. the pulse period (e-2) of flip-flop 108, is first counted in counter 120 in relation to ×2 clocks and then FF2□
The MSD output is generated by counting ×0 clocks during the pulse period of . In other words, the larger the phase error amount, the longer the output period of the flip-flop 108 becomes, and the *2 count amount also increases, so the ×0 count amount in the FF2□ period (Ti period) becomes smaller, and therefore the counter 120
The timing of MSD output becomes earlier. AND gate 1
24 serves to ensure that the MSD differential pulse always occurs within the period of FF2□. Therefore, the reset timing of the phase loop buffer counter 126 is changed depending on the magnitude of the phase error. The phase error detection counter 120 is reset at the timing of each PGC signal, i.e., once for each rotation of the head, and therefore the phase loop buffer counter 126 is reset at the timing of each PGC signal, i.e., once for each rotation of the head.
The D signal must be introduced into the velocity loop six times per each revolution of the head. For this purpose, the T SFT signal is used for controlling the clock input of buffer counter 126. (f-4) in FIG. 7 shows the waveform of this T SFT signal. This T SFT pulse is generated by the arrival of each PGA pulse, and requires one rotation of the buffer counter 126 during the T SFT pulse. That is, the buffer counter 126 is configured to hold the measured phase error six times.

The MSD output of buffer counter 126 is provided to the reset input of flip-flop 136 in six continuations of error information associated with the output of phase error detection counter 120. Therefore, the MFD output of flip-flop 136 is PG
It turns on when the A signal arrives, and has a falling timing that represents a phase error.

(f -1) in Figure 7 is the PGA of the velocity loop in Figure 5.
The output of the signal delay circuit 54 is shown, (f-2) is the output FF1 of the flip-flop 56, and (f-3) is the output of the M
FD signal is shown. Further, FIG. 8 is a waveform diagram in which the time position of the signal g in FIG. 7 is enlarged to include other signals as well.

Figure 8 (a) shows the PGA signal, (b) shows the PGB signal, (C
) is the output of the delay circuit 54 that rises in response to the PGA signal and falls after a predetermined specific time, and (d) is the output of the flip-flop 56 that is set in response to this falling and reset in response to the PGB signal. It is FF1. (e) is the MFD signal from the phase loop, and has a rising period representing a phase error due to the PGA signal.

Speed detection counter 7 reset by PGA' signal
8 counts x1 clock during this MFD signal period. That is, a phase term is introduced into the velocity loop by changing the initial value of the count value of counter 78. (f
) indicates the T SFT signal, which similarly rises in response to the PGA signal and is used for a predetermined length, that is, the phase loop buffer counter 126 rotates six times as described above.

The speed detection counter 78 also counts ×1 clock during the period of the signal FF□. As mentioned above, the period of FF1 represents the speed term. Therefore, speed detection counter 7
8 is F Fl, which means that the number of clocks corresponding to the phase and velocity terms was counted at the falling position of the signal.

FIG. 8(g) shows the Ti signal that determines the PWM period,
(h) shows an FF which is the output of the flip-flop 70 for generating PWM output. FF rises at the position of the Ti timing pulse and falls at the end of a period depending on the phase and magnitude of the velocity term.

(h) is the output FF3 of the flip-flop 58, which rises with the arrival of the PGB pulse and then continues in time <T
It falls when the i-timing pulse occurs. Figure 8(i)
rises in response to the falling of FF, and the next Ti
It shows the FF1o signal falling in response to the timing pulse. This FF. The signal is provided to AND gate 84;
It strobes the clock *O and supplies the *O clock to the clock input of the speed detection counter 78 via the OR gate 88 . In the middle of the FFlo period, the counter 78 is full-up due to the supply of the ×0 clock, and as a result, the counter 78
outputs an MSD falling edge, which resets the velocity loop buffer counter 66. This causes the MS and D edges of this buffer counter 66, thereby determining the timing of the fall position (position indicated by the arrow) of the FF2 signal. The subsequent fall position of FF2 follows the fall of the buffer counter until the arrival of the next reset pulse.

In the digital servo circuit configured as described above, the present invention attempts to automatically adjust the phase lock position, and the block diagram is shown in FIG.
Figure 0 shows the timing chart.

In the figure, when the reference signal S (phase reference pulse at terminal 102) arrives, that is, when the phase detection time ends, the content of the phase detection counter 120 is checked, the amount to be corrected is determined, and the movement amount counter 145 is set. In other words, if the rising edge of the reference signal and the rising edge of the most significant bit of the phase detection counter 120 match, there is no residual error.

A movement amount counter 145 stores how much correction is to be made according to the magnitude of this phase error.

At the same time, the direction in which the residual error is located is transferred to the moving direction flip-flop 146, and the amount of movement is added to or subtracted from the correction counter 147 during the transfer time T. Then, at the transfer time T2, the counting result of the phase detection counter 120 (phase information) and the contents of the correction counter 147 (residual error information)
The feedback information MFD to the velocity loop shown in FIG. 5 is obtained by adding and subtracting the values. At this time, the correction counter 147 stores the content of the residual error to be corrected, and it is retained as long as the power is not turned off. Therefore, once the residual error is corrected when the power is turned on, the remaining error will be corrected after that. You can instantly access lock information.

Even if the phase is locked, until the reference signal and the most significant bit of the phase detection counter 120 match, the correction counter 147 provides information to the speed loop that there is still an error. This is the translation. Therefore, even if the motor load changes due to temperature changes and the lock phase shifts, according to the present invention, the shift can be corrected by 11.
0". For abrupt phase shifts, this may be the 6th
This is the range of the phase servo shown in the figure, and the part related to so-called DC gain, which varies over time, has been improved, and as a result, we can expect an operation similar to infinite DC gain. In FIG. 9, 148 to 50 are means 1 to 1.

FIG. 11 shows a specific embodiment of the present invention, which is basically modified from the circuit shown in FIG. Therefore, it should be noted that circuit elements that are the same as those in FIG. 6 are given the same numbers as much as possible.

In the present invention, a variable delay circuit (corresponding to the residual error correction counter 147 in the case of FIG. 11) is inserted between the monomulti 106 and the flip-flop 108 in FIG.
The time constant of the monomulti in FIG. 11 is halved compared to that in FIG. 6, and the residual error correction counter takes over the remaining half of the time.

When the VTR itself is energized for the first time, the servo loop is not yet stable, so the counter 147 is always preset to the design center value. That is, the switch 200 is a power switch, and the automatic correction loop is activated after a period of time determined by the monomulti 202 after the switch 200 is operated. Therefore, the output of the switch 200 and the output of the monomulti 202 are connected to each other via the AND circuit 204.
type flip-flop 206. On the other hand, the output of this D-type flip-flop 206 is subsequently applied to the data terminal of a D-type flip-flop 208, and a PGC' pulse is applied to the clock terminal of each of the flip-flops 206 and 208. If the outputs of flip-flops 206 and 208 are labeled FX, FX, respectively, the outputs FX1 and FX, respectively, will be synchronized to the PGC' pulse. The state of this portion becomes clear from the waveform diagram in FIG.

In FIG. 12, A is the PGC' pulse, B is the output of the switch 200, C is the output of the monomulti 202, D is the output of the AND circuit 204, and E and F are the outputs FX□ and F, respectively.
Indicates X2. In addition, the negative output of the flip-flop 206, that is, the FX signal, gates the PGC' pulse in the AND circuit 210, and until the monomulti 202 rises, that is, during the servo unstable period, the PGC' pulse controls the correction counter. The design center value (10000000) is preset loaded. On the other hand, the output of the monomulti 106 is made up of a predetermined time by two D-type flip-flops 212 and 214 and a counter 216. Counter 216 is the output of flip-flop 214, i.e. TJS
From the rising edge of the T signal, the AND circuit 218 strobes and counts x2 clocks, and resets the flip-flop 214. Also, the carry output of the counter 216 is 1.
A decoder 220 is provided to create the time before the bit, and a monomulti 220 is provided to create the time before the bit.
22 are provided.

This situation becomes clear from the waveform diagram in FIG.

That is, in Fig. 13, A is the PGC' pulse, B is the monomulti 1
06, C indicates the TJST signal, D indicates the TEND signal, and E indicates the TNXT signal. The TJST, TEND, and TNXT signals are all synchronized with ×2 clock.
Further, the TEND signal and the TNXT signal each indicate a width of one clock of *2 clocks. When there is no residual error, the MSD of the error correction counter 147 is x as shown in FIG.
After counting two clocks, the flip-flop 108 is triggered via the differentiation circuit 224 when the pulse TJST falls exactly at the center.

Further, the residual error is detected by checking the state of the phase detection counter. That is, flip flop 10
The contents of the counter 120 at the falling (reset) timing of
Latch to 28.

The decoder 151 is applied to the flip-flop 226 when the number is 130 or more, and when the number is 126 or less to the flip-flop 228.
The output from the flip-flop 226 is output from the counter 147 and latched. If the contents of the counter 120 are between 127 and 129, it is assumed that there is no residual error and no error correction is performed. The output of the flip-flop 228 means to decrease the count clock of the counter 147 by one.The respective signals are supplied to an AND gate 230 and a Nant gate 232. The output of the gate 232 and the TJ ST multiplied signal are supplied to an AND circuit 234, and the output of the AND circuit 234 supplies ×2 clocks to the counter 147 via an OR circuit 236 and an AND circuit 238.
A loop works so that 0 is always driven to the center of the setting,
The error correction counter 147 will deviate from the design center by that amount.

Furthermore, in the above explanation, the operation of the error correction counter 147 is performed one bit at a time from the center of the design, but the residual error may deviate significantly at the start of measurement, and in that case, FX, FX, At a time defined by
If you give it to , you can speed up the tracking.

[Brief explanation of drawings]

Figure 1 is a schematic block diagram showing a conventional servo circuit.
Figure 2 is an operational waveform diagram of the circuit in Figure 1, Figure 3 is a waveform diagram for explaining the operation of a general digital error detector, and Figure 4 is a waveform diagram of the phase servo, which is the subject of the present invention. Explanatory diagram,
5 and 6 are block diagrams of the digital servo circuit targeted by the present invention, FIGS. 7 and 8 are operational waveform diagrams, and FIG. 9 is a block diagram showing the basic configuration of the present invention.
0 is a waveform diagram for explaining the operation, FIG. 11 is a block diagram showing one embodiment of the present invention, and FIGS. 12 and 13 are waveform diagrams for explaining a part of the operation. In the figure, 66 is a speed loop buffer counter, and 70 is PW.
A flip-flop for M generation, 120 a phase detection power counter, and 147 a residual error correction counter. Patent applicant Sony Corporation (5b

Claims (1)

[Claims] storage means for holding phase difference information between a reference signal and a controlled signal obtained as the rotating body rotates, and a phase of the controlled signal having a constant relationship with the phase of the reference signal according to the output of the storage means. In the servo circuit for controlling the rotation of the rotating body so that and variable phase control means for electrically correcting the phase of the reference signal or the controlled signal according to the output of the means.