JPS6217879A - Data memory device - Google Patents

Abstract

PURPOSE:To separate, compress and store input data and to use storage capacity effectively by separating the input data into common item data and the other data and comparing the common item data with data obtained at the preceding sampling time. CONSTITUTION:A data separating/compressing circuit 1 separates input data into common item data and the other data so that these data can be assembled to a data format to be reproduced at the time of output, and stores the former and the latter data in a common part data memory 2 and an individual data memory 3 respectively. The common item data stored in the memory 2 are the range information of respective channels, unit information and header information and the data stored in the memory 3 are time data and measuring data of respective channels. A data synthesizing circuit 4 returns the data separated, compressed and stored in the memories 2, 3 by the data separating and compressing circuit 1 to the original input format.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a data storage W1 device, and more particularly to an improvement in data storage capacity.

(Prior art) A device (for example, a hybrid recorder, etc.) that outputs measurement time, measurement value, etc. at a certain fixed time interval.
retrieve data via the bus interface from
Data storage devices, such as semiconductor memories and floppy disk devices, which can store this data and read out the stored data as desired are well known.

(Problem to be Solved by the Invention) However, in conventional data storage devices of this type, data retrieved via the bus interface was stored in the same data format; The problem is that it requires a large amount of memory capacity.

In view of these points, an object of the present invention is to provide a hybrid (
When storing output data from a nocoder, etc., the data is separated and compressed to store a large amount of data in a limited storage capacity, and when reading data, the separated and compressed data is converted back to the original. It is an object of the present invention to provide a data storage device that can be reproduced and output in a data format and that can effectively utilize storage capacity.

(Means for Solving the Problems) In order to achieve such an object, the present invention includes a common part data memory for storing only the common item data, and a common part data memory for storing only the common item data. The method for individual data to overturn data memory is to separate the input data into the common term [] data and data outside of it, and make it into a common term]. If the data does not match the fI sampling data (2-1)
Move that data to sample point 1 and pair it with data.
: Send to the common part data memory, and items other than the jt continuous 4-item data are sent to the lean pull point j~・1'
- A data separation/compression circuit that sends out the data to the individual data menu, and the ripple point data read from the common section data menu and the data read from the individual data menu. Compare the sample points 1 to 1 data that have been read, and if they match, set the data read this time as the common item [1 data, and if there is a match, set the data read last time as the common item data. , this ring 1) is characterized in that it is equipped with an f-data synthesis circuit which synthesizes the data read from the memory for individual data and reproduces it in the original data format and outputs it.

(Example) The present invention will be described in detail below using the drawings. FIG. 1 is a conceptual block diagram showing an embodiment of a data storage device according to the present invention. In the figure, 1 is a data separation/compression circuit, 2
is memory for common part data, 3 is memory for individual data, 4 is memory for individual data.
is a data synthesis circuit.

The data separation/compression circuit 1 receives data from a hybrid recorder, data logger, etc. for a certain period of time T (se
c) Multi-channel voltage, temperature, etc. data DL for each
is input. Each series of data sets input every T time interval has the contents as shown in FIG. 2, for example,
Date, time to 11, and header information for each channel,
It consists of range information, data, and unit information.

YY of the date data represents year information, MM represents month information, DD represents day information, HH of time data represents hour information, MM represents minute information, and SS represents second information.

In each channel data, H is header information, R is range information, DDDDD is data, and U is unit information. The header information includes the following range, data, 11
This information indicates that this is the final channel of Sera 1-.

FIG. 3 is a diagram showing the flow of 1 data. Data separation/
The compression circuit 1 separates input data, for example in the format shown in FIG. The data is assembled into a data format, and the former is stored in the common part data memory 2, and the latter is stored in the individual data memory 3.

The common item data stored in the common part data memory 2 are date data, range information for each dial, unit information, and header information, and the data stored in the individual data memory 3 is as follows. These are time data and measurement data for each channel. Year, month, and day data changes values less often than time data, so by storing only the correspondence of measurement data that changes, the storage capacity can be saved. In addition, the range and unit data will remain constant if the settings are not changed on the data output device side while the data is being stored, and if they are changed, a new range corresponding to the changed data will be displayed. Only unit data is stored, and if there is no change, it is not stored.

In the data synthesis circuit 4, when data is output, the data separation/compression circuit 1 compresses the data in the memories 2 and 3 by -1 and returns the stored data to the original input format.

Here, the data separation/compression circuit 1 and the data synthesis circuit 4 will be described in more detail. FIG. 4 is a diagram showing the flow of data when data is stored and when it is played back in two cases: storage of frj times and storage of variability.
FIG. 6 is a detailed configuration diagram of the data separation/compression circuit 1 shown in FIG. 1, and FIG. 6 is a poly configuration diagram showing details of the data synthesis circuit shown in FIG.

In FIG. 5, 11 is a roll circuit to the sampling controller 1, which controls other circuits such as receiving sampling data. 12 is a data separation/compression circuit, which separates Dn data and Mn data in FIG.
When the data, Mn data is an ASCII code or the like, it is compressed into binary data. Dn is data that is stored only when the header, range, unit, etc. change, while Mn is a measured value that is stored every time.

13 is a delay buffer, which is a latch that holds the previous value of Dn data. 14 is a comparator which compares the output of the delay buffer 13 and the output of the data separation/compression circuit 12, and when they are equal, outputs a write signal to the memory 2 and commands from 1 to 1 of the address counter 1G.

The data (Dn + Mn) sampled by the summing control circuit 11 is separated and compressed in the data compression circuit 12, and Mn is unconditionally written to the memory 3 and r )n is compared with the previous value Dn-ma in the comparator 14, and if they do not match, the sample pointer data (sample NO.
) are both written to memory 2. As shown in Figure 4, sample No. 0 to 4 data MO~M4
is paired with the sample pointer data and stored in memory 3.
are stored sequentially. On the other hand, data Dn is data D for sample No. O. is stored in memory 2 as a pair of sample No. 0, but since sample No. 1 to 3 are the same, they are not stored, and when the data changes to sample No. 4, Dl) That sample No. , and are stored in the memory 2 in pairs.

Address counter 16 is incremented when writing to memory 2 is performed, and address counter 17 is incremented when writing to memory 3 is performed.

The delay buffer 13 latches the current data Dn so that it can be used as the previous data in the next cycle.

The data separated and compressed in this way and stored in the memory is reproduced into the original data format by the data synthesis circuit. In the data synthesis circuit of Fig. 6, 4
1 is a comparator which compares the sample pointer data from memories 2 and 3, and when they match, gives a lattice signal to the Dn data latch 42 and gives a run 1~ signal to the Dn atto 1 counter 46. Reference numeral 45 denotes a data output controller 1 to roll circuit, which controls all circuits in response to a data output request. 44 is a data reproducing circuit which reproduces and synthesizes the Dn and Mn data into the original data format from the output data of the data latch/1.2.4-3.

In the data synthesis circuit having such a configuration, the data output layers 1 to 45, which have received the data output request, send necessary control signals to each section. Comparator 41 compares sample pointer data read from memories 2 and 3 (addresses are specified by address counters 46 and 47), outputs a latch signal when they match, and latches Dn data into the ON data latch. do. At the same time, a count signal is given to the address counter 46 to increment it.

On the other hand, for data Mn, the data output control circuit 45
The data latch 43 is latched each time by a control signal from the address counter 17, and the address counter /17 is also incremented each time. The output data of the data latches 42 and 43 is led to the data reproducing circuit 44, and is synthesized as it is.
The data is reproduced in the original data format as shown in FIG. This playback data passes through the data output control circuit 45 (
) is output.

As described above, data is divided into R1 and Dn.
If there are consecutive duplicates, memory usage efficiency is improved by compressing the data to avoid duplicate storage in memory.

It should be noted that the present invention is not limited to the embodiments, and the same object can be achieved with other configurations and the same effects can be expected.

(Effects of the Invention) As described above, according to the present invention, by compressing the stored data, it is possible to reproduce the original data with a storage capacity smaller than that of the stored data. It is possible to make the device smaller and increase its capacity.

[Brief explanation of drawings]

FIG. 1 is a conceptual configuration diagram showing an embodiment of a data storage device according to the present invention, FIG. 2 is a diagram for explaining data input at every T time interval, and FIG. 3 is a diagram showing the flow of data. Figure 4 is a diagram showing the flow of data during data storage and playback, and Figure 5 is the data separation/compression circuit 1 in Figure 1.
6 is a block diagram showing the details of the data synthesis circuit shown in FIG. , 3...Memory for individual data, 4...Data synthesis circuit, 11...Sampling control circuit, 12...Data separation/compression circuit, 13...Delay buffer 1.14.41... Comparator, 15...
・Gate, 16.46...Dn address counter,
17゜47...Mn address counter, 42.43
...Data latch, 44...Data regeneration circuit, 45
...Data output controller (~roll circuit. \... C one gourd

Claims (1)

[Scope of Claims] In a data storage device configured to be capable of writing and reading a large amount of data consisting of a large amount of data and item data common to the data, for storing only the common item data. a memory for common part data, a memory for individual data for storing data other than the common item data, and a memory for separating the input data into the common item data and other data, and storing the common item data. Only when the data does not match the data from the previous sampling, the data is paired with the sample point data and sent to the common section data memory, and data other than the common item data is paired with the sample point data. a data separation/compression circuit that sends the sample point data to the individual data memory; and a data separation/compression circuit that compares the sample point data read from the common data memory with the sample point data read from the individual data memory; If they match, the data read this time is used as common item data, and if they do not match, the data read last time is used as common item data, and this item data and the data read from the individual data memory are combined. A data storage device comprising a data synthesis circuit that reproduces and outputs data in its original format.