JPS62183190A - Manufacture of semiconductor pressure transducer - Google Patents
Manufacture of semiconductor pressure transducerInfo
- Publication number
- JPS62183190A JPS62183190A JP2480086A JP2480086A JPS62183190A JP S62183190 A JPS62183190 A JP S62183190A JP 2480086 A JP2480086 A JP 2480086A JP 2480086 A JP2480086 A JP 2480086A JP S62183190 A JPS62183190 A JP S62183190A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- etching
- mask
- impurity concentration
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Pressure Sensors (AREA)
- Weting (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
本発明は、−導電型の層の中に他導電型の層からなるゲ
ージ抵抗が設けられる厚さの薄い起歪部を有する半導体
圧力変換器の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor pressure transducer having a thin strain-generating portion in which a gauge resistor made of a layer of a different conductivity type is provided in a layer of a negative conductivity type.
従来、圧力感度のばらつきが小さく、特性のそろった均
一な板厚を有する圧力変換器起歪部を得るためには、第
3図に示す如く、不純物を高濃度に添加した単結晶シリ
コン基板1の片面に、低不純物濃度層2をエピタキシャ
ル成長させ、この低不純物濃度層2に異なる導電形のひ
ずみゲージ3を形成し、ひずみゲージ3に相対する基板
面の周辺部に電気的絶縁性を有する膜、例えば酸化膜4
を設け、この絶縁膜上にニッケル(Ni)、クロム(C
r)を含有する金(Au)の金属膜5を被着してこれを
エツチングマスクとし、エツチング液6中において高不
純物濃度シリコン基板1と、これに対向して置かれた白
金陰電掻7間に電B8により直流電圧を印加することに
より電気化学的にエツチングし、不純物濃度境界面11
でエツチングを停止させ、均一な板厚を有する圧力変換
器起歪部を得ようとしていた。
このような起歪部成形方法では、第4図fa+に示すよ
うに、エツチングの進行に伴い凹部12の底面13のほ
かに側面14からも電流が流れ、凹部形成が進行するこ
とになるが、それとともに電流供給路の抵抗が増加し、
その増加率は周辺部より中央部の方がより大きくなる傾
向がある。この抵抗増加率の差により、供給される電流
は中心部より周辺部の方が大きく、エツチングの速度も
電流の大きさに比例して周辺部の方が大きくなる傾向が
あり、凹部形成の進行によりさらにその傾向が強まる。
その結果凹部底面13中央部近辺より周辺部の方が早く
エツチングされることにより、最終的には第3図中)の
如く濃度境界面11へ周辺部の方が早く到達することに
なり、周辺部の凹部形成がその時点で停止する。同時に
凹部底面13の中央部も、周辺部が濃度境界面11へ到
達したために電流供給を遮断されてもはやエツチングが
進行せず、エツチング残り15が発生することになる。
このエツチング残り15は、その径が最終的な凹部11
の径の約174〜115、残り厚さは基板lの厚さの5
〜10%程度にばらつき、またその形状も一様でないの
でこれにより圧力感度のばらつきやその他の圧力変換器
特性のばらつきを生じていた。Conventionally, in order to obtain a strain sensitive part of a pressure transducer having small variations in pressure sensitivity, uniform characteristics, and uniform plate thickness, a single crystal silicon substrate 1 doped with impurities at a high concentration is used as shown in FIG. A low impurity concentration layer 2 is epitaxially grown on one side of the substrate, a strain gauge 3 of a different conductivity type is formed on this low impurity concentration layer 2, and an electrically insulating film is formed on the periphery of the substrate surface facing the strain gauge 3. , for example, oxide film 4
nickel (Ni) and chromium (C) are provided on this insulating film.
A metal film 5 of gold (Au) containing r) is deposited and used as an etching mask, and a high impurity concentration silicon substrate 1 and a platinum negative electrode 7 placed opposite thereto are coated in an etching solution 6. Electrochemical etching is performed by applying a DC voltage between the electrodes B8 and the impurity concentration boundary surface 11.
The etching was stopped at this point in order to obtain a pressure transducer strain-generating part with a uniform plate thickness. In such a method of forming a strain-generating part, as the etching progresses, current flows not only from the bottom surface 13 of the recess 12 but also from the side surface 14, and the formation of the recess progresses. At the same time, the resistance of the current supply path increases,
The rate of increase tends to be greater in the center than in the periphery. Due to this difference in resistance increase rate, the supplied current is larger at the periphery than at the center, and the etching speed tends to be larger at the periphery in proportion to the magnitude of the current, resulting in the progress of recess formation. This tendency will become even stronger. As a result, the peripheral part is etched faster than the vicinity of the central part of the bottom surface 13 of the recess, so that the peripheral part eventually reaches the concentration boundary surface 11 earlier as shown in FIG. The formation of the recess in the part stops at that point. At the same time, since the peripheral portion of the central portion of the bottom surface 13 of the concave portion has reached the concentration boundary surface 11, the current supply is cut off, and etching no longer progresses, resulting in an etched residue 15. This etching residue 15 has a diameter that is the final recess 11.
The diameter of the board is approximately 174-115 mm, and the remaining thickness is approximately 5 mm of the thickness of the substrate l.
The variation is about 10%, and the shape is also not uniform, which causes variation in pressure sensitivity and other variations in pressure transducer characteristics.
本発明は、起歪部の板圧が均一で、圧力感度にばらつき
がなく、特性のよくそろった半導体圧力変換器の製造方
法を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor pressure transducer in which the plate pressure of the strain-generating portion is uniform, the pressure sensitivity is uniform, and the characteristics are uniform.
本発明は基板上に基板より低い不純物濃度を有する層を
積層し、低不純物濃度層と逆の側の基板面に絶縁膜を介
して被着される金属膜よりなるマスクを設け、エツチン
グ液中においてマスク被着表面に対向配置された電極と
基板間に直流電圧を印加し、電気化学的に不純物濃度境
界面までエツチングして起歪部のための凹部を形成する
際に、基板面のマスクが被着されない領域に中央部より
周辺部が厚く、エツチング液により基板より小さいエツ
チング速度でエツチングされる絶縁膜を被着するもので
あり、これによって凹部形成部では周辺部で中央部より
不純物濃度境界面にエツチングが到達する時間が遅れる
ため中央部で濃度境界面にエツチングが到達するまで電
流供給が遮断されず、上記の目的を達成することができ
る。マスクが被着されない領域に設けられる絶縁膜が、
金属膜と共にマスクを構成する絶縁膜の延長部であるこ
とは本発明の実施の上で極めて有効である。In the present invention, a layer having an impurity concentration lower than that of the substrate is laminated on a substrate, a mask made of a metal film is deposited on the opposite side of the substrate surface from the low impurity concentration layer through an insulating film, and the layer is etched in an etching solution. When a DC voltage is applied between the substrate and an electrode placed opposite to the surface to which the mask is applied, electrochemical etching is performed to the impurity concentration interface to form a concave portion for the strain-generating portion. An insulating film that is thicker at the periphery than at the center and etched by an etching solution at a slower etching rate than the substrate is deposited on areas where the concave portion is not deposited, and as a result, the impurity concentration is lower at the periphery than at the center in the recess formation area. Since the time for etching to reach the boundary surface is delayed, the current supply is not cut off until the etching reaches the concentration boundary surface in the central region, making it possible to achieve the above objective. The insulating film provided in the area where the mask is not applied is
It is extremely effective for the present invention to be an extension of the insulating film that constitutes the mask together with the metal film.
以下図を引用して本発明の詳細な説明する。
各図の第3図と共通の部分には同一の符号が付されてい
る。第1図において、有効なピエゾ抵抗効果が得られる
結晶方位を有し、例えば10”/cc以上のひ素、ある
いは10”/cc以上のアンチモンを含む高濃度単結晶
シリコン基板1の片面に、最終的に必要とする起歪部の
厚さ分だけ10”/cc以下の低不純物濃度層2をエピ
タキシャル成長させ、この低不純物濃度層に異なる導電
形の層からなるひずみゲージ3を形成し、このひずみゲ
ージに相対する基板他面に電気的絶縁性を有する膜、例
えば酸化膜4を約IIrI&の厚さで全面に設け、さら
にその上に旧、 Crを14〜30%含有するAuから
なる金属膜5を被着する。この金r%Wj!5のひずみ
ゲージ3に相対する中央部を、形成すべき凹部に相当す
る径りの領域を除去し、次に下側の酸化膜を1/40以
上に相当する寸法、例えば1/3 ・Dの径の領域だ
け除去する。
この様な構成のシリコン基板1を第2図の如く弗酸と純
水の混合比率が1:9のエツチング液6中に浸漬し、液
中に設置された白金陰電極7間に電源9により数ボルト
の直流電圧を印加して電気化学的にエツチングする。こ
の時のエツチング速度は高不純物濃度シリコン基板1が
約2−7分。
酸化膜4が約0.02−7分であり、金属膜5によって
覆われない酸化膜4がエツチングされ、シリコン基@1
0表面が露出するのに約50分の時間を必要とする。一
方、シリコン基板1表面の酸化膜4によって覆われてい
ない部分は、約50分間に第5図(alに示すように約
100μの深さまでエツチングされ、さらに進行して第
5図(blの如(中央部においては周辺部より早く濃度
境界面11へ到達する。
周辺部は引つづきエツチングされ、最終的には第5図(
C1の如く周辺部も濃度境界面11へ到達し凹部12の
形成は終了する。低不純物濃度層2のエツチング速度は
高濃度シリコン基板1に比べて約1/100程度と充分
に小さいので、周辺部より早く濃度境界面11へ到達し
た中央部は実質的にそれより深くならず、平坦な底面1
3が生ずる。
このようにして形成された凹部12は、底面にエツチン
グ残りが全くなく、均一な板厚を存する起歪部が得られ
る。
第6図ta+〜(C1は本発明の他の実施例における酸
化膜4の設置を示し、第6図(al、(blにおいては
凹部形成領域内の酸化膜4の厚さを周辺部から中央部に
向かって漸減され、第6図(C1においては、中央部に
も酸化膜4を設け、周辺部酸化膜厚が中央部より厚くな
るよう階段状としたものである。いずれの場合も上記実
施例の起歪部と同じ様な起歪部が得られる0以上の各実
施例において、酸化膜4の代わりに他の絶縁膜を用いる
こともできるが、エツチング液によって基板より低いエ
ツチング速度でエツチングされることが必要である。
なお実際の製造工程においては、1枚のシリコンウェハ
に多数の凹部12を同時に形成し、ウェハを切断して分
割し、多数の圧力変換器用半導体基体を同時に製作する
。
【発明の効果]
本発明によれば、高不純物濃度基板とその上に積層され
た低不純物濃度層との間の濃度境界面におけるエツチン
グ停止を利用し、電気化学的に半導体圧力変換器起歪部
のための凹部を形成する際に、マスクに覆われない凹部
形成領域にも中心部より周辺部より厚くなるような絶縁
膜を被着し、その絶縁膜のエツチングされる時間の差を
利用してエツチングが中央部において周辺部より早く不
純物濃度境界面に到達させることにより、凹部外面中央
部のエツチング残りを完全に避けることができる。この
結果、均一な板厚を有する起歪部が作成され、圧力感度
のばらつきが小さく、特性のよくそろった半導体圧力変
換器を製造することができる。The present invention will be described in detail below with reference to the drawings. The same parts in each figure as in FIG. 3 are given the same reference numerals. In FIG. 1, a high-concentration single-crystal silicon substrate 1 has a crystal orientation that provides an effective piezoresistance effect, and contains, for example, 10"/cc or more of arsenic or 10"/cc or more of antimony. A low impurity concentration layer 2 of 10"/cc or less is epitaxially grown by the thickness of the strain-generating part required for the purpose of the invention, and a strain gauge 3 made of layers of different conductivity types is formed on this low impurity concentration layer. On the other side of the substrate facing the gauge, an electrically insulating film, for example, an oxide film 4, is provided on the entire surface with a thickness of about IIrI, and on top of that is a metal film made of Au containing 14 to 30% Cr. 5. At the central part of this gold r%Wj!5 facing the strain gauge 3, a region with a diameter corresponding to the recess to be formed is removed, and then the lower oxide film is reduced to 1/40. Only a region corresponding to the above dimensions, for example, a diameter of 1/3 . A DC voltage of several volts is applied from a power source 9 between the platinum negative electrodes 7 installed in the liquid to perform electrochemical etching.At this time, the etching rate is approximately 2-7 minutes.The oxide film 4 is etched for about 0.02-7 minutes, and the oxide film 4 not covered by the metal film 5 is etched, and the silicon base @1 is etched.
It takes approximately 50 minutes for the 0 surface to be exposed. On the other hand, the portion of the surface of the silicon substrate 1 that is not covered by the oxide film 4 is etched to a depth of approximately 100 μm as shown in FIG. (The central part reaches the concentration boundary surface 11 earlier than the peripheral part. The peripheral part continues to be etched and finally reaches the concentration boundary surface 11 as shown in Fig. 5.
As indicated by C1, the peripheral portion also reaches the concentration boundary surface 11, and the formation of the recessed portion 12 is completed. Since the etching rate of the low impurity concentration layer 2 is sufficiently low, approximately 1/100 of that of the high concentration silicon substrate 1, the central portion, which reaches the concentration boundary surface 11 earlier than the peripheral portion, is not substantially deeper than that. , flat bottom 1
3 occurs. The concave portion 12 formed in this manner has no etching residue on the bottom surface, and a strain-generating portion having a uniform thickness can be obtained. Figure 6 ta+~(C1 shows the installation of the oxide film 4 in another embodiment of the present invention, and Figure 6 (al, (bl) shows the thickness of the oxide film 4 in the recess formation region from the periphery to the center. The oxide film 4 is also provided in the central part in FIG. In each of 0 or more examples in which a strain-generating portion similar to the strain-generating portion of the example is obtained, another insulating film can be used instead of the oxide film 4, but it can be etched with an etching solution at a lower etching rate than the substrate. In the actual manufacturing process, a large number of recesses 12 are simultaneously formed on one silicon wafer, the wafer is cut and divided, and a large number of semiconductor substrates for pressure transducers are simultaneously manufactured. [Effects of the Invention] According to the present invention, a semiconductor pressure transducer can be electrochemically fabricated by utilizing etching stoppage at the concentration interface between a high impurity concentration substrate and a low impurity concentration layer laminated thereon. When forming a recess for a strain-generating part, an insulating film that is thicker in the center than in the periphery is deposited on the recess forming area that is not covered by the mask, and the etching time of the insulating film is determined by the difference in etching time. By using etching to reach the impurity concentration boundary surface earlier in the center than in the periphery, it is possible to completely avoid etching residue in the center of the outer surface of the recess.As a result, a strain-generating part with a uniform plate thickness This makes it possible to manufacture semiconductor pressure transducers with small variations in pressure sensitivity and well-matched characteristics.
第1図は本発明の一実施例における起歪部作成前の基板
の断面図、第2図は第1図の基板の起歪部作成のための
エツチング時の断面図、第3図は従来の起歪部作成のた
めのエツチング時の断面図、第4図は従来の方法での起
歪部作成エツチングの進行状態を順次示す断面図、第5
図は第2図に示したエツチングの進行状態を順次示す断
面図、第6図は本発明の三つの異なる実施例における酸
化膜設置の状態を示す断面図である。
1:シリコン基板、2:低不純物濃度層、3:ひずみゲ
ージ、4二酸化膜、5:金属膜、6:エツチング液、7
:陰電極、11:不純物濃度境界面。
酋゛コア人41;ヱ上 、b エフ 忙X/
第1図
第2図
第3図
第4図
第5図
第6醒FIG. 1 is a cross-sectional view of a substrate before creating a strain-generating portion in an embodiment of the present invention, FIG. 2 is a cross-sectional view of the substrate shown in FIG. 1 during etching to create a strain-generating portion, and FIG. 3 is a conventional etching process. FIG. 4 is a sectional view showing the progress of etching to create a strain-generating portion using a conventional method; FIG.
The figures are cross-sectional views sequentially showing the progress of etching shown in FIG. 2, and FIG. 6 is a cross-sectional view showing the state of oxide film installation in three different embodiments of the present invention. 1: Silicon substrate, 2: Low impurity concentration layer, 3: Strain gauge, 4 Dioxide film, 5: Metal film, 6: Etching solution, 7
: cathode, 11: impurity concentration interface.゛Core people 41; ヱ上、b ふ Busy X/ Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Awakening
Claims (1)
層を積層し、低不純物濃度層と逆の側の基板面に絶縁膜
を介して被着される金属膜よりなるマスクを設け、エッ
チング液中においてマスク被着面に対向配置された電極
と前記基板間に直流電圧を印加して電気化学的に不純物
濃度境界面までエッチングして起歪部のための凹部を形
成する際に、半導体基板面のマスクが被着されない領域
に中央部より周辺部が厚く、エッチング液により半導体
基板より小さいエッチング速度でエッチングされる絶縁
膜を被着することを特徴とする半導体圧力変換器の製造
方法。 2)特許請求の範囲第1項記載の方法において、マスク
が被着されない領域に被着される絶縁膜が金属膜と共に
マスクを構成する絶縁膜の延長部であることを特徴とす
る半導体圧力変換器の製造方法。[Claims] 1) A metal film formed by laminating a layer having an impurity concentration lower than that of the substrate on a semiconductor substrate, and depositing an insulating film on the surface of the substrate opposite to the low impurity concentration layer. A mask is provided, and a DC voltage is applied in an etching solution between an electrode placed opposite to the surface to which the mask is applied and the substrate to electrochemically etch to the impurity concentration interface to form a concave portion for a strain-generating portion. A semiconductor pressure conversion method characterized by depositing an insulating film on a region of the semiconductor substrate surface where a mask is not deposited, which is thicker at the periphery than at the center and is etched by an etching solution at a lower etching rate than the semiconductor substrate. How to make the utensils. 2) A semiconductor pressure conversion method according to claim 1, characterized in that the insulating film applied to the area where the mask is not applied is an extension of the insulating film that constitutes the mask together with the metal film. How to make the utensils.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2480086A JPS62183190A (en) | 1986-02-06 | 1986-02-06 | Manufacture of semiconductor pressure transducer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2480086A JPS62183190A (en) | 1986-02-06 | 1986-02-06 | Manufacture of semiconductor pressure transducer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62183190A true JPS62183190A (en) | 1987-08-11 |
Family
ID=12148270
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2480086A Pending JPS62183190A (en) | 1986-02-06 | 1986-02-06 | Manufacture of semiconductor pressure transducer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62183190A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06268238A (en) * | 1993-03-10 | 1994-09-22 | Nippondenso Co Ltd | Semiconductor strain sensor and manufacture thereof |
-
1986
- 1986-02-06 JP JP2480086A patent/JPS62183190A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06268238A (en) * | 1993-03-10 | 1994-09-22 | Nippondenso Co Ltd | Semiconductor strain sensor and manufacture thereof |
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