JPS62190859A - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS62190859A
JPS62190859A JP61034672A JP3467286A JPS62190859A JP S62190859 A JPS62190859 A JP S62190859A JP 61034672 A JP61034672 A JP 61034672A JP 3467286 A JP3467286 A JP 3467286A JP S62190859 A JPS62190859 A JP S62190859A
Authority
JP
Japan
Prior art keywords
substrate
electrode
diode
layer
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61034672A
Other languages
Japanese (ja)
Inventor
Masayoshi Saito
斎藤　正吉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP61034672A priority Critical patent/JPS62190859A/en
Publication of JPS62190859A publication Critical patent/JPS62190859A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To remove a current by a power terminal by forming the same conductivity type diffused layer as a diffused layer for forming a diode on the periphery of an overvoltage input protective diode, and connecting the diffused layer with a voltage source of a reverse voltage level to a substrate potential to efficiently absorb the current before affecting the influence to a peripheral circuit. CONSTITUTION:A peripheral diffused layer 2 is connected through an electrode 4 with a reverse level to a power line. When a semiconductor substrate 6 is made of an N-type semiconductor, the diffused layers 1, 2 are of P-type, the substrate 6 is connected with a high potential (VDD), and the electrode 4 is connected with a low potential (VSS). When a voltage higher than the VDD is applied from an input terminal to an electrode 3, a protective diode becomes a forward bias so that a current flows to the substrate 6, a current flows to the layer 2 due to the operation of a parasitic PNP transistor generated at this time and is absorbed to the VSS. Similarly, when the substrate 6 is made of a P-type semiconductor, the layers 1, 2 become N-type, and the current flowing to the layer 2 is absorbed to a power source.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はダイオード構造により過電圧入力を吸収して入
力回路を保護するＭＯ８型半導体装置に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an MO8 type semiconductor device that protects an input circuit by absorbing overvoltage input using a diode structure.

従来の技術 従来の過電圧入力に対する保護ダイオードの場合、ダイ
オードを通じて流れ込んだ電流はダイオードを構成する
基板を通じて電源に吸収されていた。2. Description of the Related Art In the case of a conventional overvoltage input protection diode, the current flowing through the diode is absorbed into the power supply through the substrate constituting the diode.

発明が解決しようとする問題点 このような従来の方式では、保護用ダイオードの周辺に
他の回路部分があると、ダイオードに流れ込んだ電流が
基板を通じて電源に流れ込む時に、ダイオード周辺の回
路部分の電位を変動させ、誤動作を生じさせてしまうこ
とがあった。Problems to be Solved by the Invention In such a conventional method, if there are other circuit parts around the protective diode, when the current flowing into the diode flows into the power supply through the board, the potential of the circuit parts around the diode will change. This could lead to fluctuations and malfunctions.

問題点を解決するための手段 本発明は、上記問題点を解決するため、過電圧入力保護
用ダイオードの周辺に、ダイオードを構成する拡散層と
同じ導電形の拡散層を設け、その拡散層を基板電位と逆
の電圧レベルの電圧源に接続した半導体装置である。Means for Solving the Problems In order to solve the above problems, the present invention provides a diffusion layer of the same conductivity type as the diffusion layer constituting the diode around the overvoltage input protection diode, and connects the diffusion layer to the substrate. This is a semiconductor device connected to a voltage source with a voltage level opposite to the potential.

作用 本発明によると、過電圧入力はダイオードおよびその周
辺の拡散層を通じて基板電位と逆の電圧源に流出し、し
たがって、その電流は周辺の回路に影響を及ぼす前に効
率よく吸収し、電源端子によって除去されるものである
。According to the present invention, the overvoltage input flows through the diode and its surrounding diffusion layer to a voltage source opposite to the substrate potential, so that the current is efficiently absorbed before affecting the surrounding circuitry and is dissipated by the power supply terminal. It is something that will be removed.

実施例 第１図は本発明の過電圧保護用半導体装置の一実施例の
平面パターン図であり、第２図はその構造断面図である
。１は入力保護ダイオードの拡散層、２は新たに設けた
電流吸収用の拡散層、３゜４は電極、６は絶縁膜、６は
半導体基板である。Embodiment FIG. 1 is a plan pattern diagram of an embodiment of the overvoltage protection semiconductor device of the present invention, and FIG. 2 is a structural sectional view thereof. 1 is a diffusion layer of an input protection diode, 2 is a newly provided diffusion layer for current absorption, 3.4 is an electrode, 6 is an insulating film, and 6 is a semiconductor substrate.

そして、周辺の拡散層２は電極４を通じて、電源ライン
とは逆レベルに接続されている。The peripheral diffusion layer 2 is connected to the power supply line through an electrode 4 at a level opposite to that of the power supply line.

半導体基板６がＮ型半導体の場合を例にとると。Let us take as an example the case where the semiconductor substrate 6 is an N-type semiconductor.

拡散層１及び２はＰ型である。基板６は高い電位（以下
ＶＤＤという）に接続され、電極４は低い電位（以下ｖ
ＳＳという）に接続されている。Diffusion layers 1 and 2 are of P type. The substrate 6 is connected to a high potential (hereinafter referred to as VDD), and the electrode 4 is connected to a low potential (hereinafter referred to as v
SS).

入力端子からの電極３にＶＤＤより高い電圧が加わシ、
保護ダイオードが順方向バイアスとなって基板６に電流
が流れ込む。この時に発生する寄生ＰＮＰ　）ランジス
タの作用によシ、拡散層２に電流が流れ込みｖＳＳに吸
収される。When a voltage higher than VDD is applied to electrode 3 from the input terminal,
The protection diode becomes forward biased and current flows into the substrate 6. Due to the action of the parasitic PNP transistor generated at this time, current flows into the diffusion layer 2 and is absorbed by vSS.

同様に半導体基板６がＰ型半導体の場合は拡散層１と２
はＨ型となシ、保護ダイオードが順方向にバイアスされ
た時に発生する寄生？１ＰＮ）ランジスタの作用により
、拡散層２に流れ込んだ電流は電源に吸収される。Similarly, if the semiconductor substrate 6 is a P-type semiconductor, the diffusion layers 1 and 2
Is it H type? Is it parasitic that occurs when the protection diode is forward biased? 1PN) Due to the action of the transistor, the current flowing into the diffusion layer 2 is absorbed by the power supply.

発明の効果 以上のように本発明によれば、簡単な構成により、入力
保護ダイオードに流れ込む過電圧入力の電流を、基板を
通して電源に吸収すると同時に。Effects of the Invention As described above, according to the present invention, with a simple configuration, the overvoltage input current flowing into the input protection diode can be absorbed into the power supply through the substrate and at the same time.

寄生トランジスタのコレクタを通して電源に吸収するこ
とができ、周辺回路部分への影響が低減され、実用的に
きわめて有効である。It can be absorbed into the power supply through the collector of the parasitic transistor, reducing the influence on peripheral circuits, and is extremely effective in practice.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例における平面パターン図、第
２図はその構造断面図である。 １・・・・・・入力保護ダイオード拡散層、２・・・・
・・新たに設けた拡散層、３・・・・・・入力端子から
の電極、４・・・・・・寄生トランジスタコレクタ部電
極、６・・・・・・絶縁膜、６・・・・・・半導体基板
。FIG. 1 is a plane pattern diagram of an embodiment of the present invention, and FIG. 2 is a structural cross-sectional diagram thereof. 1... Input protection diode diffusion layer, 2...
...Newly provided diffusion layer, 3... Electrode from input terminal, 4... Parasitic transistor collector electrode, 6... Insulating film, 6... ...Semiconductor substrate.

Claims (1)

【特許請求の範囲】[Claims] 電流を流し込むための拡散によるダイオードを有し、前
記ダイオードの周辺に、前記ダイオードの拡散と同導電
形で基板電位と逆の電位源に接続された拡散層を設けた
ことを特徴とする半導体装置。A semiconductor device comprising a diffusion diode for flowing current, and a diffusion layer provided around the diode, the diffusion layer having the same conductivity type as the diffusion of the diode and connected to a potential source opposite to the substrate potential. .
JP61034672A 1986-02-18 1986-02-18 semiconductor equipment Pending JPS62190859A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61034672A JPS62190859A (en) 1986-02-18 1986-02-18 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61034672A JPS62190859A (en) 1986-02-18 1986-02-18 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS62190859A true JPS62190859A (en) 1987-08-21

Family

ID=12420915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61034672A Pending JPS62190859A (en) 1986-02-18 1986-02-18 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS62190859A (en)

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