JPS62190865A - Semiconductor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device that exhibits a memory function by temporarily storing charge in a capacitor.

Prior Art Conventional temporary storage devices, e.g. dynamic random
In access memory (DRAM), one electrode of the capacitor is at a fixed potential unrelated to the signal line, such as VDD or ground potential (for example, Sunami et al. IEDM (Il, D, M,) P2O3). .

Problems to be Solved by the Invention As memories become more highly integrated, the area of memory cells is reduced, resulting in smaller capacitance and smaller read signals. There is a limit to how thin a gate insulating film can be made, and it becomes difficult to manufacture a trench capacitor if the trench is made deeper, so it is difficult to increase the capacitance.

The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor memory device that is highly integrated and has a memory cell with a large read signal.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention has a structure in which both electrodes of a capacitor for storing charges are connected to a bit line and a bit line through respective switch transistors. However, this is inconsistent with the highly integrated method of using two switch transistors instead of the conventional one.
To solve this problem, a trench was formed in the semiconductor substrate, and switch transistors were formed on both sides of the trench. Furthermore, in order to achieve higher integration, a capacitor is also formed within the groove.

Note that when only one electrode of the capacitor is connected to the bit line and the other is connected to a fixed potential, the magnitude of the read signal is approximately four times as large as when both electrodes are connected to the bit line. Become.

Effects The present invention has the effect of increasing the read signal and increasing the degree of integration due to the above-mentioned structure.

Embodiment FIG. 1 is a sectional view showing an embodiment of the semiconductor memory device of the present invention. 1 is a P-type semiconductor substrate, 2 is a groove formed parallel to each other in the substrate 1, 3 is a gate insulating film with a thickness of about 101 m formed on the bottom and side surfaces of the groove, and 4 is made of polycrystalline silicon. a first conductor; 5 and 7 are insulating films;
6 is a second conductor made of polycrystalline silicon and has a thickness of about 0.5 microns; 11a, 12 & 11t), 12b
are the n-type first to fourth diffusion layers that become the source or drain,
8 and 8' are contacts formed on the upper surfaces of the island regions 13 and 13', and bit lines 9 and 9' made of aluminum wiring and the second and fourth diffusion layers 12&, 1
2b is electrically connected here. 1st. A switch transistor (SW-TR) 100 is formed by the second diffusion layers 111L and 122L and the second conductor 6. Fourth diffusion r@11b.

12b and the second conductor 6 to connect the 5W-TR101 to the first
The diffusion layer 11a, the gate insulating film 3, and the first conductor 4 each constitute a storage capacitor 102.

FIG. 2 is its equivalent circuit diagram. capacitor 102 and b
3W between it (bit) line, bi, t (bit) line
-TRs 100 and 101 are interposed, and the writing and reading of signals is controlled by the word line W. The first conductor 4 is a diffusion layer 11b of 5W-TR101.
When the 5W-TRs 100 and 101 are in the OFF state, the capacitor 102 is completely separated from the BIT line, and in the ON state, both electrodes of the capacitor are connected to the BIT line.

Effects of the Invention As described above, according to the present invention, a semiconductor memory device with a high integration density and a high read signal level can be obtained. A high read signal level means that the signal can be reliably read without malfunction, making the present invention extremely useful.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a memory cell in an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram corresponding to FIG. 1. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 3... Gate insulating film, 4.6... First and second conductors buried in trench 2, 11 &... ...N-type first diffusion layer, 11b...N-type third diffusion layer, 12a
......N-type second diffusion layer, 12b...
N-type fourth diffusion layer, 100° 101... switch transistor, 102... storage capacitor.

Claims (1)

[Claims] A plurality of parallel grooves formed on one main surface of a semiconductor substrate of a first conductivity type, an island region sandwiched between them, and a plurality of parallel grooves formed in one main surface of a semiconductor substrate of a first conductivity type, and a plurality of parallel grooves buried in the grooves sequentially from the bottom of the grooves with a gate insulating film interposed therebetween. a first diffusion layer of a second conductivity type formed across the bottom of the groove and one side surface; The first diffusion layer is a second diffusion layer of a second conductivity type separated by the second conductor, and a second diffusion layer on the other side of the groove and in contact with the first conductor. a third diffusion layer of a second conductivity type; a fourth diffusion layer of a second conductivity type formed over the other side surface of the groove and the upper surface of the island region and separated from the third diffusion layer by the second conductor; a diffusion layer, the second or fourth diffusion layer being connected to a bit line or a bit line.