JPS62193473A - Simultaneous coinciding circuit for television signal - Google Patents

Simultaneous coinciding circuit for television signal

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Publication number
JPS62193473A
JPS62193473A JP61035687A JP3568786A JPS62193473A JP S62193473 A JPS62193473 A JP S62193473A JP 61035687 A JP61035687 A JP 61035687A JP 3568786 A JP3568786 A JP 3568786A JP S62193473 A JPS62193473 A JP S62193473A
Authority
JP
Japan
Prior art keywords
signal
circuit
output
input
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61035687A
Other languages
Japanese (ja)
Inventor
Kazuhiko Ueda
和彦 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP61035687A priority Critical patent/JPS62193473A/en
Publication of JPS62193473A publication Critical patent/JPS62193473A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To take out a high SN, line sequential signal while reducing the fluctuation of a hue at every line and color error at a color edge and coinciding simultaneously by providing a circuit that coincides and takes out a signal in which the input of a delay element at an initial step and the output of the delay element at the succeeding step are added, and the output of the delay element with a switching signal at every cycle period. CONSTITUTION:A signal (d) is obtained by subtracting a signal (a) inputted to a terminal 13 from the output signal (c) of a 1H delay circuit 16. The signal (d) is changed to a noise signal (e) passing through a non-linear amplifier 18, and a signal (g), the noise component of which is reduced by adding the signal (e) on the signal (a) at an adder 14, and a signal (h) in which the signal (c) of the 1H delay circuit 16 is averaged, can be obtained, and also, a signal (b) from which the noise component is reduced at a 1H delay circuit 15, can be obtained, and the signals (h), and (b) are coincided and taken out at a switch circuit 10.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はテレビジョン信号の同時化回路に係り、例えば
カラーテレビジョンカメラにおいて線順次時分割多重さ
れた信号をライン毎に同時化して取出す回路に関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a television signal synchronization circuit, for example, a circuit for synchronizing line-by-line time-division multiplexed signals in a color television camera and extracting the signals. Regarding.

(従来技術) 第5図は一般のカラーテレビジョンカメラの同時化回路
の一例のブロック系統図を示す。その前面に第6図(A
)に示す補色形色フィルタ1aを設けられた’fli@
素子1における光電変換部に蓄積された各色に対する電
荷はインクラインCCD内で垂直方向に2画素ずつ混合
され、奇数フィールド及び偶数フィールド毎に組合わU
を異ならせて取出される。
(Prior Art) FIG. 5 shows a block diagram of an example of a synchronization circuit of a general color television camera. In front of it is Figure 6 (A
) is equipped with the complementary color filter 1a shown in 'fli@
The charges for each color accumulated in the photoelectric conversion section in element 1 are mixed vertically in two pixels in an ink-line CCD, and combined for each odd field and even field.
are taken out with different values.

撮像素子1からの信号は低域フィルタ2にて輝度信号y
wとされて加算器3(、:供給される一方、サンプルホ
ールド回路41.42に供給されて180°位相の異な
るサンプリングパルスにてホールドされ、サンプルホー
ルド回路41からは例えば(W+Ye )及び(W+C
V )が、サンプルホールド回路42からは例えば(G
+Cy)及び(G+Ye )が取出され、減算器5にて
減算されてR信号及びB信号が取出され、減算器6゛か
ら色差信号(R−Y)、(B−Y)(時分割多重信号)
が線順次に出力される。
The signal from the image sensor 1 is passed through a low-pass filter 2 to produce a luminance signal y.
w and is supplied to the adder 3 (,:). On the other hand, it is supplied to sample and hold circuits 41 and 42 and held with sampling pulses with a 180° phase difference, and from the sample and hold circuit 41, for example, (W+Ye) and (W+C
For example, the sample and hold circuit 42 outputs (G
+Cy) and (G+Ye) are taken out, subtracted by the subtractor 5 to take out the R signal and B signal, and the subtractor 6' takes out the color difference signals (R-Y), (B-Y) (time division multiplexed signal )
are output line-sequentially.

色差信号(R−Y)、(B−Y)は低域フィルタ7を介
して同時化回路8に供給され、ここで1H遅延回路9及
びライン毎に切換えられるスイッチ回路10にて同時化
されて取出され、平衡変調回路11にて変調クロマ信号
とされ、加算器3にて輝度信@YWと加算されてコンポ
ジット映像信号とされ、出力端子12より取出される。
The color difference signals (R-Y) and (B-Y) are supplied to a synchronization circuit 8 via a low-pass filter 7, where they are synchronized by a 1H delay circuit 9 and a switch circuit 10 that is switched for each line. The signal is taken out, converted into a modulated chroma signal by the balanced modulation circuit 11, and added with the luminance signal @YW by the adder 3 to form a composite video signal, which is taken out from the output terminal 12.

ところで、一般に、第6図(A)に示す補色形色フィル
タ1aを用いた単板カラーテレビジョンカメラの方が、
第6図(B)に示す原色形色フィルタ1bを用いたそれ
に比して色信号の輝度信号に対するSN比が悪いことが
知られているが、次に、これを説明する。
By the way, in general, a single-chip color television camera using the complementary color filter 1a shown in FIG.
It is known that the SN ratio of the color signal to the luminance signal is worse than that using the primary color filter 1b shown in FIG. 6(B), but this will be explained next.

インクラインCODのダイナミックレンジは垂直(CO
Dの1段当りの)転送電荷量により定まり、いま、この
電荷量をQ maxとする。発生する電荷量がQmax
/k(但し、定数に=3〜4)となる様に入射光を調整
し、この状態を標準状態とする。標準状態において、第
6図(A)に示す補色形色フィルタ1aのフィールド蓄
積モードCCDの隣接2画素のレベル(lli度信号レ
ベル)は、(W+Ye ’)+ (G+CV ) =4fJ +2r +2b = 2− Qllax /に となる。ここで、簡単のために、照明及びCODの分光
特性をフラット((1:  r:  b=1 :1 :
1)にすれば、上式より g =r =b =Qmax /4に となる。従って、色信号の復調量は、例えばR信号では
、 R= (W+Ye )−(G+Cy )2r =(lax/2k          (1)となる。
The dynamic range of incline COD is vertical (CO
It is determined by the amount of transferred charge (per stage of D), and this amount of charge is now set as Q max. The amount of charge generated is Qmax
/k (however, constant = 3 to 4), and this state is defined as a standard state. In the standard state, the level (lli degree signal level) of two adjacent pixels of the field accumulation mode CCD of the complementary color filter 1a shown in FIG. 6(A) is (W+Ye')+(G+CV)=4fJ+2r+2b=2 - Qllax / becomes. Here, for simplicity, the spectral characteristics of illumination and COD are flattened ((1: r: b=1:1:
1), then g = r = b = Qmax /4 from the above equation. Therefore, the amount of demodulation of the color signal is, for example, R signal: R=(W+Ye)-(G+Cy)2r=(lax/2k (1)).

一方、第6図(B)に示す原色形色フィルタ1bのフレ
ーム蓄積モードCODについて同様に計算すると、隣接
2画素のレベル(Ii度信号レベル)は、 G+R=g+r = 2− Qmax /に となり、り:r:b=1:1:1とすると、g =r 
−b =Qmax /に となり、従って、色信号の復調量は、例えばR信号では
、 R=r =Qmax/k           ■となる。
On the other hand, if the frame accumulation mode COD of the primary color filter 1b shown in FIG. 6(B) is calculated in the same way, the level of two adjacent pixels (Ii degree signal level) will be G+R=g+r=2-Qmax/, If ri:r:b=1:1:1, then g=r
-b=Qmax/, and therefore, the demodulation amount of the color signal is, for example, R=r=Qmax/k (2).

COD転送電荷の1パケット当りの発生するノイズがフ
ィールド蓄積及びフレーム蓄積の間において差がなけれ
ば、色信号のSN比は復調信号電荷量に比例し、上記計
算では、(1)式、■式より、補色形色フィルタ1aを
用いた方が6dBSN比が悪くなる。
If there is no difference in the noise generated per packet of COD transfer charges between field accumulation and frame accumulation, the SN ratio of the color signal is proportional to the amount of demodulated signal charge, and in the above calculation, Equation (1), Equation (2) Therefore, the 6 dBSN ratio becomes worse when the complementary color filter 1a is used.

この様な問題を解決する方法として本出願人は先に特願
昭60−194289号「テレビジョン信号の同時化回
路」を出願した。
As a method for solving such problems, the present applicant previously filed Japanese Patent Application No. 194289-1989 ``Television Signal Synchronization Circuit''.

これにより線順次色差信号をS/N高く同時化できるが
、同時化回路の問題として、同時化された信号の垂直方
向の位相が合っていないことである。これはイメージヤ
出力がR−Yの時はB−Y信号を1H前の信号で補間す
る為に生ずる問題である。例えば、第7図に示すような
垂直方向のエツジではR−Y、B−Y信号の垂直方向の
位相がそろっていない為に、疑似色信号が発生する。ま
た、第8図に示すように色相が一定で明るさが除徐に変
化するような被写体のR像時には走査線毎の色相にぶれ
が生ずる。
This allows line-sequential color difference signals to be synchronized with a high S/N ratio, but a problem with the synchronization circuit is that the vertical phases of the synchronized signals do not match. This problem occurs because when the imager output is R-Y, the B-Y signal is interpolated with a signal 1H earlier. For example, at a vertical edge as shown in FIG. 7, a false color signal is generated because the vertical phases of the R-Y and B-Y signals are not aligned. Further, as shown in FIG. 8, in the case of an R image of a subject in which the hue is constant and the brightness changes gradually, blurring occurs in the hue of each scanning line.

(発明が解決しようとする問題点) このように、従来の回路では補色形色フィルタ1aを用
いると色信号の変調度が下がり、色信号のSN比が低下
する問題点があった。
(Problems to be Solved by the Invention) As described above, the conventional circuit has a problem in that when the complementary color filter 1a is used, the degree of modulation of the color signal decreases, and the S/N ratio of the color signal decreases.

さらに、同時化の際、補間される信号が1H前の信号で
ある為、同時化回路の出力R−Y、B−Y信号には垂直
方向の位相差が生じ、その結果、エツジに偽似の色を生
じたり、なめらかな彩度変化に対してもライン毎に色相
変化が生じる問題点があった。
Furthermore, during synchronization, since the interpolated signal is a signal from 1H earlier, a vertical phase difference occurs between the R-Y and B-Y signals output from the synchronization circuit, resulting in false edges. However, there are problems in that hue changes occur line by line even when there is a smooth change in saturation.

本発明は、補色形色フィルタを用いた場合でも線順次色
差信号をSN比高く、同時化して取出し、かつ、同時化
の際の色疑似信号の発生を低減し得るテレビジョン信号
の同時化回路を提供することを目的とする。
The present invention provides a television signal synchronization circuit that can synchronize and extract line-sequential color difference signals with a high signal-to-noise ratio even when a complementary color filter is used, and can reduce the generation of color pseudo signals during synchronization. The purpose is to provide

(問題点を解決するための手段) 第1図において、1日遅延回路15.16は時分割多重
信号を構成するーの信号の期間に相当する遅延量をもち
時分割多重信号の縦続接続した手段、減算器17は1H
N延回路15の入力と1日遅延回路16の出力とを減算
する演算手段、ノンリニアアンプ18は演算手段の出力
を1日遅延回路15の入力にへカー出力特性がノンリニ
アに変化する手段、加算器25は遅延素子15の入力と
遅延素子16の出力を加算して平均化する手段、スイッ
チ回路10は縦続接続された遅延素子の各入力を2周期
毎の切換信号にて同11:1化して取出す手段の各−実
施例である。
(Means for Solving the Problem) In Fig. 1, the one-day delay circuits 15 and 16 have delay amounts corresponding to the period of signals composing the time division multiplexed signal, and are connected in cascade of the time division multiplexed signals. Means, subtractor 17 is 1H
A calculation means for subtracting the input of the N delay circuit 15 and the output of the one-day delay circuit 16, a non-linear amplifier 18, a means for changing the output characteristic non-linearly by inputting the output of the calculation means to the input of the one-day delay circuit 15, and addition. The switch circuit 10 adds and averages the input of the delay element 15 and the output of the delay element 16, and the switch circuit 10 equalizes each input of the cascaded delay elements to 11:1 using a switching signal every two cycles. 3A and 3B are examples of means for extracting the data.

(作 用) 1日遅延回路16の出力信号C(第2図(C))から端
子13に入来した信号a (同図(A))を減算して信
号d (同図(D))を得、信号dをノンリニアアンプ
18を通してノイズ信号e (同図(E))とし、加算
器14にて信号aに信号eを加算してノイズ成分を軽減
された信号g (同図(G))と1日遅延回路16のC
を平均化した信号h 〈同図(H))を得ると共に11
−(遅延回路15にてノイズ成分を軽減された信@b 
(同図(B))を得、スイッチ回路10にて信号り、b
を同時化して取出す。
(Function) The signal a (FIG. 2 (A)) input to the terminal 13 is subtracted from the output signal C (FIG. 2 (C)) of the one-day delay circuit 16 to obtain the signal d (FIG. 2 (D)). The signal d is passed through the nonlinear amplifier 18 to become a noise signal e ((E) in the same figure), and the adder 14 adds the signal e to the signal a to create a signal g ((G) in the same figure) with the noise component reduced. ) and C of 1-day delay circuit 16
A signal h ((H) in the same figure) is obtained by averaging the
-(Signal whose noise component is reduced by the delay circuit 15 @b
((B) in the same figure) is obtained, and a signal is sent from the switch circuit 10,
are simultaneously extracted.

(実 施 例) 第1図は本発明回路の一実施例のブロック系統図を示す
。同図において、端子13に入来した色差信号(B−Y
)及び(R−Y)(第5図示の低域フィルタ7の出力で
、色差信号(B−Y)を第2図(A)に示す)は後述の
加算器14を介して1日遅延回路15.16に順次供給
され、丁H遅延回路16から信号C(同図(C))が取
出され、信号Cは減算器17に供給されて色差信号(B
−Y)から減算される。色差信号は本来強い垂直相関性
を有し、かつ、線順次信号の繰返しは2日であるので、
減算器17に供給された2つの色差信号は垂直相関性が
強く、これにより、減算器17からは非相関性のノイズ
の反転成分及び色差信号の非相関成分(垂直エツジ)か
らなる信号d (同図(D))が取出される。
(Embodiment) FIG. 1 shows a block system diagram of an embodiment of the circuit of the present invention. In the figure, the color difference signal (B-Y
) and (RY) (the output of the low-pass filter 7 shown in FIG. 5, the color difference signal (B-Y) is shown in FIG. 15 and 16, the signal C ((C) in the same figure) is taken out from the H delay circuit 16, and the signal C is supplied to the subtracter 17 to produce a color difference signal (B
−Y). Color difference signals inherently have strong vertical correlation, and line sequential signals are repeated every two days.
The two color difference signals supplied to the subtracter 17 have a strong vertical correlation, so that the subtracter 17 outputs a signal d ( (D)) is taken out.

信号dは例えば第3図(A)に示す入力−出力特性を持
つノンリニアアンプ18に供給され、これにより、色差
信号の非相関成分が抑圧された信号e (第2図(E)
)とされる。これを実質上ノイズの逆相成分とみなす。
The signal d is supplied to a nonlinear amplifier 18 having the input-output characteristics shown in FIG. 3(A), for example, and thereby the signal e (FIG. 2(E)) in which the uncorrelated components of the color difference signals are suppressed is generated.
). This is essentially considered to be a negative phase component of noise.

このノイズ成分eは加算器14にて色差信号(B −Y
’)に加算され、これにより、加算器14からはノイズ
成分eを低減された色差信号(B−Y)’  (同図(
G))が取出され、1日遅延回路16の出力Cと加算器
25で加算され、さらに1/2乗算鼎26でレベルが半
分にされてスイッチ回路10に供給される。
This noise component e is sent to the adder 14 as a color difference signal (B - Y
'), and as a result, the adder 14 outputs the color difference signal (B-Y)' with the noise component e reduced ((
G)) is taken out and added to the output C of the one-day delay circuit 16 in an adder 25, and then its level is halved in a 1/2 multiplier 26 and supplied to the switch circuit 10.

また、1日遅延回路15からは、上記色差信号(B−Y
)’ と同様にノイズ成分を低減された色差信号(R−
Y)’が取出され、スイッチ回路10に供給される。
Further, from the one-day delay circuit 15, the color difference signal (B-Y
)', the color difference signal (R-
Y)' is taken out and supplied to the switch circuit 10.

スイッチ回路10では従来回路と同様にライン切換信号
によりライン毎にスイッチングが行なわれ、色差信号(
B−Y)’ 、(R−Y)’が同時化されて端子191
.192より取出される。
In the switch circuit 10, switching is performed for each line by a line switching signal as in the conventional circuit, and the color difference signal (
B-Y)' and (RY)' are synchronized and connected to terminal 191.
.. 192.

なお、ノンリニアアンプ18の入力−出力特性は第3図
(B)に示すものでもよく、この場合、ノンリニアアン
プの出力であるノイズ成分は第2図(F)に示す如くで
あり、上記実施例のものと略同様にノイズ成分を低減さ
れた色差信号を得ることができる。
Note that the input-output characteristics of the nonlinear amplifier 18 may be as shown in FIG. 3(B). In this case, the noise component which is the output of the nonlinear amplifier is as shown in FIG. 2(F). It is possible to obtain a color difference signal in which the noise component is reduced in substantially the same way as in the case of the above method.

また、端子13に入来する時分割多重信号が2H毎に反
転する信号であれば、第1図中減算器17の代わりに加
算器を用いる。
Further, if the time division multiplexed signal input to the terminal 13 is a signal that is inverted every 2H, an adder is used in place of the subtracter 17 in FIG.

ところで、第1図に示す端子13に同時化信号が入来し
、1日遅延回路15の出力から信号を取出さず、加算器
14の出力又は遅延回路16の出ら信号を取出す構成の
回路はいわゆる巡回形ノイズリデューサである。第3図
(A>、(B)に示す入力−出力特性の原点付近の傾斜
をKとし、1H遅延に対応する単位遅延演算子を71と
すれば、入力信号に2H周期の垂直相関がある場合の伝
達関数H(Z)は、 H(Z)= (1−K)/ (1−KZ′2)=(1−
K)(1+KZ′2 +に2 Z −4+−KnZ−2n+−)・・・・・・
■ となる。信号は振幅平均、ランダム雑音は電力相の平方
根となるので、信号の伝達関数Hs  (K)、雑音の
伝達関数Hn(K)は、 Hs  (K)= (1−K)(1+に+に2 +に3
+・・・+l(n+・・・) = 1 Hn  (K)= ((1−k )(1+に2+に’+
に&  +・・・+K 2n+・・・))丁=J (1
−、K> / (1+K) となる。
By the way, there is a circuit in which a synchronization signal is input to the terminal 13 shown in FIG. is a so-called cyclic noise reducer. If the slope near the origin of the input-output characteristics shown in Figure 3 (A>, (B) is K, and the unit delay operator corresponding to the 1H delay is 71, then there is a vertical correlation of 2H periods in the input signal. The transfer function H(Z) in this case is H(Z) = (1-K)/ (1-KZ'2) = (1-
K) (1+KZ'2 + to 2 Z -4+-KnZ-2n+-)...
■ It becomes. Since the signal is the amplitude average and the random noise is the square root of the power phase, the signal transfer function Hs (K) and the noise transfer function Hn (K) are Hs (K) = (1-K) (1+ to + 2 + 3
+...+l(n+...) = 1 Hn (K)= ((1-k)(1+ to 2+'+
ni & +...+K 2n+...)) ding=J (1
−, K> / (1+K).

従って、垂直相関のある信号に対しては、Kを1に近づ
けることによって雑音を低減し得、一方、垂直相関のな
い信号に対しては、Kを小にすることにより前記(3)
式中KZ″2以下の項を無視し得、垂直方向の画像のぼ
けを少なくし得る。
Therefore, for signals with vertical correlation, noise can be reduced by making K close to 1, while for signals without vertical correlation, by reducing K,
In the equation, the term below KZ″2 can be ignored, and the blur of the image in the vertical direction can be reduced.

また、同時化は第9図のように欠落した信号を上下のラ
インの平均値で補間している。従って、補間された信号
と補間されなかった信号の垂直方向の位相がずれておら
ず、第8図に示すようなライン毎の色相変化は生じにく
い。
Furthermore, in synchronization, as shown in FIG. 9, missing signals are interpolated using the average value of the upper and lower lines. Therefore, the interpolated signal and the non-interpolated signal are not out of phase in the vertical direction, and the hue change for each line as shown in FIG. 8 is unlikely to occur.

さらにまた、第7図に示すような色エツジに対してもそ
のエラー量は半減しており、両側に分散されるので、第
10図に示すように視覚的に目立ちにく1なる。
Furthermore, the error amount for color edges as shown in FIG. 7 is reduced by half, and is distributed on both sides, making it less visually noticeable as shown in FIG. 10.

第4図は本発明回路の他の実施例のブロック系統図を示
し、同図中、第1図と同一構成部分には同一番号を付し
てその説明を省略する。端子13に入来した色差信号は
可変利得アンプ20にて利得(1−K)を乗ぜられ、こ
の出力は可変利得アンプ22にて利得Kを乗ぜられた1
日遅延回路16の出力と加算器21にと加算されて11
1遅延回路15、スイッチ回路10に供給される。
FIG. 4 shows a block system diagram of another embodiment of the circuit of the present invention, in which the same components as in FIG. 1 are given the same numbers and their explanations will be omitted. The color difference signal input to the terminal 13 is multiplied by a gain (1-K) in a variable gain amplifier 20, and this output is multiplied by a gain (1-K) in a variable gain amplifier 22.
The output of the day delay circuit 16 and the adder 21 are added to 11
1 delay circuit 15 and switch circuit 10.

この場合、1H遅延回路16の出力及び端子13に入来
した信号は減算器23にて減算され、第3図(C)の入
力−出力特性を有する絶対値回路24からは差に応じた
制御信号CI、C2が取出されて可変利得アンプ20.
22のKの値を可変する。減算器23にて得られた信号
の値が閾値を越えた時、Kが小となるように制御される
In this case, the output of the 1H delay circuit 16 and the signal input to the terminal 13 are subtracted by the subtracter 23, and the absolute value circuit 24 having the input-output characteristic shown in FIG. Signals CI and C2 are taken out and sent to a variable gain amplifier 20.
The value of K in 22 is varied. When the value of the signal obtained by the subtracter 23 exceeds the threshold value, K is controlled to be small.

その他の動作は第1図示の回路と同様であるのでその説
明を省略する。
The other operations are the same as those of the circuit shown in the first diagram, so the explanation thereof will be omitted.

(発明の効果) 本発明によれば、線順次信号をSN比高く、色相のライ
ン毎の変化や色エツジでの色エラーを少なくして同時化
して取出し得る等の特長を有する。
(Effects of the Invention) According to the present invention, line-sequential signals can be simultaneously extracted with a high signal-to-noise ratio and with fewer line-by-line changes in hue and color errors at color edges.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は夫々本発明回路の一実施例のブロッ
ク系統図及びその信号波形図、第3図は本発明回路に用
いるノンリニアアンプ及び絶対値回路の入力−出力特性
図、第4図は本発明回路の他の実施例のブロック系統図
、第5図は従来回路の一例のブロック系統図、第6図は
補色形色フィルタ及び原色形色フィルタの構成図、第7
図及び第8図は従来回路の説咀図、第9図及び第10図
は本発明回路の説明図である。 10・・・スイッチ回路、13・・・色差信号入力端子
、14.21.25・・・加算器、 15.16・・・1H遅延回路、17.23・・・減算
器、18・・・ノンリニアアンプ、 191.192・・・色差信号出力端子、20.22・
・・可変利得アンプ、 24・・・絶対値回路、 26・・・1/2乗算器(利得アンプ)、K・・・利得
。 ^  −へ 第2図 第5図 iJ6図 第7図 第8図 撞享ルK   イメージ)ライン     PI時化匡
1各土力R−Y、B−Y              
 R−V       B−Y第9図 R−Yチャンネル イメーミ出力    B−Y チャ
ンネル第10図
1 and 2 are respectively a block system diagram and its signal waveform diagram of an embodiment of the circuit of the present invention, FIG. 3 is an input-output characteristic diagram of the nonlinear amplifier and absolute value circuit used in the circuit of the present invention, and FIG. Figure 5 is a block diagram of another embodiment of the circuit of the present invention, Figure 5 is a block diagram of an example of a conventional circuit, Figure 6 is a configuration diagram of a complementary color filter and a primary color filter, and Figure 7
8 and 8 are explanatory diagrams of the conventional circuit, and FIGS. 9 and 10 are explanatory diagrams of the circuit of the present invention. 10... Switch circuit, 13... Color difference signal input terminal, 14.21.25... Adder, 15.16... 1H delay circuit, 17.23... Subtractor, 18... Nonlinear amplifier, 191.192... Color difference signal output terminal, 20.22.
...Variable gain amplifier, 24...Absolute value circuit, 26...1/2 multiplier (gain amplifier), K...Gain. ^ -To Figure 2 Figure 5 iJ6 Figure 7 Figure 8 Figure 8
R-V B-Y Figure 9 R-Y channel Image output B-Y channel Figure 10

Claims (1)

【特許請求の範囲】[Claims] テレビジョン信号に対応した一定の繰返し周期を以て時
分割多重され、該繰返し周期毎に相関を有する時分割多
重信号を同時化して取出すテレビジョン信号の同時化回
路において、上記時分割多重信号を構成する一の信号の
期間に相当する遅延量をもつ遅延素子を2個縦続接続し
た回路と、該縦続接続された遅延素子の初段の入力と後
段の出力とを減算又は加算する演算回路と、該演算回路
の出力を該縦続接続された遅延素子の入力に入力−出力
特性がノンリニアに変化する素子を介して帰還する回路
と、該初段の遅延素子の入力と後段の遅延素子の出力を
加算した信号と該初段の遅延素子の出力を上記繰返し周
期毎の切換信号にて同時化して取出す回路とよりなるこ
とを特徴するテレビジョン信号の同時化回路。
In a television signal synchronization circuit that synchronizes and extracts time-division multiplexed signals that are time-division multiplexed at a constant repetition period corresponding to the television signal and have a correlation for each repetition period, the time-division multiplexed signal is configured. a circuit in which two delay elements each having a delay amount corresponding to the period of one signal are connected in cascade; an arithmetic circuit that subtracts or adds the input of the first stage and the output of the second stage of the cascaded delay elements; A circuit that feeds back the output of the circuit to the input of the cascaded delay elements via an element whose input-output characteristics change non-linearly, and a signal that is the sum of the input of the first-stage delay element and the output of the second-stage delay element. and a circuit for synchronizing and extracting the outputs of the first-stage delay element using the switching signal for each repetition period.
JP61035687A 1986-02-20 1986-02-20 Simultaneous coinciding circuit for television signal Pending JPS62193473A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61035687A JPS62193473A (en) 1986-02-20 1986-02-20 Simultaneous coinciding circuit for television signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61035687A JPS62193473A (en) 1986-02-20 1986-02-20 Simultaneous coinciding circuit for television signal

Publications (1)

Publication Number Publication Date
JPS62193473A true JPS62193473A (en) 1987-08-25

Family

ID=12448805

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61035687A Pending JPS62193473A (en) 1986-02-20 1986-02-20 Simultaneous coinciding circuit for television signal

Country Status (1)

Country Link
JP (1) JPS62193473A (en)

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