JPS62193Y2 - - Google Patents

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Publication number
JPS62193Y2
JPS62193Y2 JP18310281U JP18310281U JPS62193Y2 JP S62193 Y2 JPS62193 Y2 JP S62193Y2 JP 18310281 U JP18310281 U JP 18310281U JP 18310281 U JP18310281 U JP 18310281U JP S62193 Y2 JPS62193 Y2 JP S62193Y2
Authority
JP
Japan
Prior art keywords
semiconductor device
thin film
antistatic
static electricity
antistatic agent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP18310281U
Other languages
Japanese (ja)
Other versions
JPS5887348U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18310281U priority Critical patent/JPS5887348U/en
Priority to EP82304114A priority patent/EP0080790A3/en
Priority to US06/412,988 priority patent/US4605574A/en
Publication of JPS5887348U publication Critical patent/JPS5887348U/en
Priority to US06/745,876 priority patent/US4656963A/en
Application granted granted Critical
Publication of JPS62193Y2 publication Critical patent/JPS62193Y2/ja
Granted legal-status Critical Current

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  • Packaging Frangible Articles (AREA)
  • Elimination Of Static Electricity (AREA)
  • Application Of Or Painting With Fluid Materials (AREA)

Description

【考案の詳細な説明】 この考案は帯電防止処理を施した半導体デイバ
イスに関するものである。
[Detailed Description of the Invention] This invention relates to a semiconductor device subjected to antistatic treatment.

ICやLSI等の半導体デイバイスは半導体の特質
から静電気に対し、非常に弱く、特にMOS型IC
は、人体に蓄積した静電気、あるいは輸送中での
他物との摩擦及び接触により発生するわずかの静
電気により瞬時にゲート破壊を越し不良になつて
しまう。また、最近の16キロビツト又は64キロビ
ツトの高性能LSIは0.2ボルトぐらいのわずかな電
圧差で作動するように設計されているので、静電
気が伝わると機能が狂つたり、ひどいときには回
路が切断されて役立たなくなつてしまう。また半
導体デイバイスの輸送ケースとして使用している
マガジンステイツクは従来金属でできており、こ
れを接地して使用していたが、自動的に半導体デ
イバイスをマガジンステイツクから出していく際
中が見えず、中の残つた個数が分らなかつた。そ
こでこれを透明なプラスチツクで作つたものを使
用しているが、このプラスチツクのマガジンステ
イツクの中で半導体デイバイスが摺動する際、静
電気が生じ半導体が破壊されるおそれがある。し
かしながら半導体の包装材にはプラスチツクが多
く使用されており、かつ半導体デイバイスそのも
のもプラスチツクで絶縁被覆しているため、摩擦
接触によつて静電気が生じ易い。例えばプラスチ
ツクチユーブの中のセラミツクDIPSでは700V、
プラスチツクトレイに並べたセラミツクDIPSで
は4000V、発泡スチロールに入れたセラミツク
DIPSでは5000V、エアーキヤツプを取除いた時
のICでは20000V、発泡プラスチツク材で包装し
たICでは11000V、包装材から修理のために取出
したICでは6000Vの静電気が生ずる。そこで半導
体デイバイスの製造の段階、保管、運搬、機器へ
の組込み、機器の作動時等の夫々の段階において
静電気防止対策がとられている。これらの対策と
しては、帯電防止用接地ボンデイング、加湿、導
電性材料の使用、帯電防止剤の使用、静電気除電
器の使用、帯電防止作業衣の着用、静電靴の使
用、導電性床の使用、放電の抑制対策が採られて
いる。しかしながらこれらの静電気防止対策は主
に半導体デイバイスを取りまく夫々の環境におい
て行なわれているもので、製造、保管、運搬等の
各々の段階で夫々設備を施さなければならず、ま
た静電気防止効果も完全なものとは言い難いもの
であつた。また半導体デイバイスの保護容器に導
電性を付与したものが使用されているが、導電性
が付与されることにより、導体の瞬時放電、誘導
帯電等の性質を付与することとなるため、半導体
の静電破壊の防止対策としては疑問があるもので
ある。
Semiconductor devices such as ICs and LSIs are extremely susceptible to static electricity due to the characteristics of semiconductors, especially MOS type ICs.
The gate can instantly break and become defective due to static electricity accumulated in the human body or a small amount of static electricity generated due to friction and contact with other objects during transportation. In addition, recent high-performance LSIs of 16 or 64 kilobits are designed to operate with a small voltage difference of about 0.2 volts, so if static electricity is transmitted to them, they may malfunction, or in severe cases, the circuit may be disconnected. It becomes useless. Additionally, the magazine stay used as a transport case for semiconductor devices has traditionally been made of metal, and has been grounded. I couldn't figure out how many pieces were left inside. Therefore, a device made of transparent plastic is used, but when a semiconductor device slides inside this plastic magazine stay, static electricity may be generated and the semiconductor may be destroyed. However, since plastic is often used in packaging materials for semiconductors, and the semiconductor devices themselves are insulated with plastic, static electricity is likely to be generated due to frictional contact. For example, ceramic DIPS in a plastic tube has a voltage of 700V.
4000 V for ceramic DIPS arranged in a plastic tray, 4000 V for ceramic DIPS arranged in a plastic tray;
DIPS generates 5,000V of static electricity, ICs with air caps removed generate 20,000V, ICs wrapped in plastic foam generate 11,000V, and ICs removed from packaging for repair generate 6,000V of static electricity. Therefore, measures to prevent static electricity are taken at each stage of semiconductor device manufacturing, storage, transportation, installation into equipment, and operation of equipment. These measures include antistatic ground bonding, humidification, use of conductive materials, use of antistatic agents, use of static eliminators, wearing antistatic work clothing, use of electrostatic shoes, and use of conductive floors. , measures are taken to suppress discharge. However, these static electricity prevention measures are mainly taken in the respective environments surrounding semiconductor devices, and equipment must be installed at each stage of manufacturing, storage, transportation, etc., and the static electricity prevention effect is not perfect. It was hard to describe it as something special. In addition, protective containers for semiconductor devices are made with conductivity, but conductivity imparts characteristics such as instantaneous discharge and inductive charging to semiconductors, so This is a questionable measure to prevent electrical damage.

この考案はこれらの点に鑑みて考案されたもの
で、従来の半導体デイバイスを取りまく環境の帯
電防止対策に代えて、半導体デイバイスそのもの
に帯電防止処理を施すことによつて、他物との摩
擦接触によつても静電気が生ぜず、それ故静電破
壊、各種機器の誤動作等が生ぜず、半導体ものも
のの機能が十分発揮できる半導体デイバイスを提
供することを目的としたもので、これによつて従
来の如く半導体の製造、運搬保管、各種機器への
組み込み時等の各段階においていちいち静電防止
対策を施すことを要せず、半導体デイバイスの取
扱いが容易となるものである。
This idea was devised in consideration of these points.Instead of conventional measures to prevent static electricity in the environment surrounding semiconductor devices, by applying antistatic treatment to the semiconductor devices themselves, it is possible to prevent frictional contact with other objects. The purpose is to provide a semiconductor device that does not generate static electricity even when exposed to electricity, and therefore does not cause electrostatic damage or malfunction of various devices, and can fully demonstrate the functions of semiconductor devices. As described above, it is not necessary to take anti-static measures at each stage of semiconductor manufacturing, transportation and storage, installation into various devices, etc., and the handling of semiconductor devices becomes easier.

この半導体デイバイスの本体はエポキシ樹脂等
のプラスチツクで被い絶縁を付与しているが、こ
の表面に帯電防止剤を施す方法としては従来、表
面塗布法及び帯電防止剤の樹脂練込法が考えられ
る。しかしながら一般的にはこれらの方法はいず
れも欠点がある。即ち表面塗布法では塗布前の樹
脂表面上の帯電状態が、塗布形成にかなり影響が
あり、帯電の分布の不均一が塗膜厚の不均一や不
連続と関係する。従つて必然的に塗膜の厚さを大
きくすることとなり、塗布工程での乾燥工程に時
間を費す等の経済的欠点が指摘され、かつ、処理
后の表面状態にベタツキ、外観の問題が生じ、耐
久性(持続性)にも問題があつた。また樹脂練込
法においては、プラスチツク材料に適合した帯電
防止剤の選択が極めて困難であり、かつ帯電防止
剤とプラスチツクとの相溶性から表面へのブリー
ド速度、ブリードの不均一等により、形成被膜は
必ずしも全表面に亘り、均一、連続な膜を形成す
るものでない。これらの被膜のばらつきにより帯
電防止効果のばらつきが生ずる。
The main body of this semiconductor device is covered with plastic such as epoxy resin to provide insulation, but the conventional methods for applying an antistatic agent to this surface include a surface coating method and a method of kneading the antistatic agent into resin. . However, in general, all of these methods have drawbacks. That is, in the surface coating method, the state of charge on the resin surface before coating has a considerable influence on the coating formation, and non-uniformity in charge distribution is related to non-uniformity and discontinuity in coating film thickness. Therefore, the thickness of the coating film inevitably increases, and economic disadvantages have been pointed out, such as the time required for the drying process during the coating process, as well as the problem of stickiness and appearance of the surface after treatment. There were also problems with durability (sustainability). In addition, in the resin kneading method, it is extremely difficult to select an antistatic agent that is compatible with the plastic material, and due to the compatibility between the antistatic agent and the plastic, the rate of bleeding to the surface, unevenness of bleeding, etc. does not necessarily form a uniform, continuous film over the entire surface. Variations in these coatings cause variations in the antistatic effect.

そこでこの考案ではこれらのものと異なり、帯
電防止剤から成る均一かつ連続した極薄膜を形成
して上記目的を達成せしめるものである。そして
この考案の構成は、極く少量の帯電防止剤を含む
薄い濃度の水溶液又は水分散液の表面張力を、フ
ツ素系界面活性剤により30dyne/cm25℃以下に
したものを適宜の方法で煙霧状にし、このエアロ
ゾルの粒径5μ以下に選択したものを半導体デイ
バイスの本体及び各端子の外表面に付着させて、
帯電防止剤から成る均一かつ連続した極薄膜を該
外表面に形成せしめた帯電防止処理を施した半導
体デイバイスである。
Therefore, in this invention, unlike these methods, a uniform and continuous ultra-thin film made of an antistatic agent is formed to achieve the above object. The structure of this device is that the surface tension of a dilute aqueous solution or aqueous dispersion containing a very small amount of antistatic agent is reduced to 30 dyne/cm25℃ or less using a fluorine-based surfactant, and then atomized using an appropriate method. This aerosol with a particle size of 5μ or less is applied to the main body of the semiconductor device and the outer surface of each terminal,
This is a semiconductor device that has been subjected to antistatic treatment in which a uniform and continuous ultra-thin film made of an antistatic agent is formed on the outer surface.

以下この考案の一実施例を図について説明す
る。
An embodiment of this invention will be described below with reference to the drawings.

1は半導体デイバイス、2は半導体デイバイス
1の本体で、この本体2はエポキシ樹脂等の合成
樹脂で被われている。3は本体2の両側から多数
本突出した端子、4はこれら本体2及び端子3の
外表面に被われた均一かつ連続した、帯電防止剤
から成る極薄膜である。この極薄膜は本出願人が
先に提出した特願昭56−143817号(特開昭58−
45237号公報)における極薄膜の構成と同様であ
る。即ち極く少量の帯電防止剤を含む薄い濃度の
水溶液又は水分散液の表面張力をフツ素系界面活
性剤によつて30dyne/cm25℃以下にしたもの
を、適宜の方法で煙霧状とし、このエアロゾルの
粒径5μ以下のものに選択したものを上記半導体
デイバイス1の外表面にさらし、吸着させる。こ
れにより粒子は凝集せず、外表面に拡がり、粒子
が微細なことと相俟つて水分は急速に気化し、膜
厚400mμ以下、即ち可視光線波長以下の厚さの
帯電防止剤から成る極薄膜が均一にまんべんなく
半導体デイバイス1の外表面に形成されたもので
ある。第3図は半導体デイバイス1の外表面に形
成した極薄膜4の拡大断面図を示し、半導体デイ
バイス1の本体2の外表面2aの約1μ以下の微
細な凹凸2bの表面細部にまで、極薄膜4が被わ
れ、連続して形成されている。
1 is a semiconductor device, 2 is a main body of the semiconductor device 1, and this main body 2 is covered with a synthetic resin such as epoxy resin. 3 is a large number of terminals protruding from both sides of the main body 2; 4 is a uniform and continuous ultra-thin film made of an antistatic agent that covers the outer surfaces of the main body 2 and the terminals 3; This ultra-thin film was previously filed in Japanese Patent Application No. 56-143817 (Japanese Unexamined Patent Publication No. 58-1989).
This is similar to the configuration of the ultra-thin film in Publication No. 45237). That is, a dilute aqueous solution or aqueous dispersion containing a very small amount of antistatic agent has a surface tension of 30 dyne/cm25°C or less using a fluorine-containing surfactant, and is made into a fume by an appropriate method. An aerosol selected to have a particle size of 5 μm or less is exposed to the outer surface of the semiconductor device 1 and adsorbed. As a result, the particles do not agglomerate and spread over the outer surface, and in combination with the fineness of the particles, moisture evaporates rapidly, forming an ultra-thin film made of antistatic agent with a thickness of less than 400 mμ, that is, less than the wavelength of visible light. are uniformly and evenly formed on the outer surface of the semiconductor device 1. FIG. 3 shows an enlarged sectional view of the ultra-thin film 4 formed on the outer surface of the semiconductor device 1. 4 are covered and formed continuously.

この考案は以上の構造であり、これを透明なプ
ラスチツクのマガジンステイツク等の包装材に入
れても、この考案及び包装材の双方に静電気の発
生が生じない。従つて従来の如く包装材に導電性
を付与したりする等の処理が不要となる。これは
この考案が半導体デイバイス1の外表面に均一か
つ連続した極薄膜4を形成しているため他物と摩
擦接触しても静電気が生ぜず、帯電防止効果を長
期にわたつて持続できるものである。この様にこ
の考案では半導体デイバイスそのものに帯電防止
効果を施しているため、製造、保管、運搬、種々
の機器への組み込み等の各段階で静電気防止対策
を施さなくてよい。しかもこの考案では半導体デ
イバイス1の本体2及び端子3を極薄膜4で被つ
ているため、夫々の素地が直接外気に接触せず、
半導体デイバイス1の置かれた雰囲気乃至は環境
に影響されない。またこの考案の半導体デイバイ
ス1は端子3をハンダ付けによつて機器へ接続す
るため、ハンダ熱によつて端子3の該箇所の極薄
膜4がとび端子3の導体が露出するため機器への
接続の障害とならない。また極薄膜4は半導体デ
イバイス1の全周を被つているが端子3相互の導
通はない。即ち極薄膜4の面方向に対しては抵抗
率が高い(実測値1014オーム/cm)ため極薄膜4
を通つて隣接相互の端子3が導通しない。
This device has the above-described structure, and even if it is placed in a packaging material such as a transparent plastic magazine stick, static electricity will not be generated in either the device or the packaging material. Therefore, there is no need for conventional treatments such as imparting conductivity to the packaging material. This is because this invention forms a uniform and continuous ultra-thin film 4 on the outer surface of the semiconductor device 1, so that static electricity is not generated even when it comes into frictional contact with other objects, and the antistatic effect can be maintained for a long time. be. In this way, in this invention, since the semiconductor device itself has an antistatic effect, there is no need to take antistatic measures at each stage of manufacturing, storage, transportation, and integration into various devices. Moreover, in this invention, the main body 2 and terminals 3 of the semiconductor device 1 are covered with an extremely thin film 4, so that the respective substrates do not come into direct contact with the outside air.
It is not affected by the atmosphere or environment in which the semiconductor device 1 is placed. In addition, since the semiconductor device 1 of this invention connects the terminal 3 to the equipment by soldering, the ultra-thin film 4 of the terminal 3 is blown away by the heat of the solder and the conductor of the terminal 3 is exposed. does not become an obstacle. Although the extremely thin film 4 covers the entire circumference of the semiconductor device 1, there is no electrical conduction between the terminals 3. In other words, since the resistivity is high in the plane direction of the ultra-thin film 4 (actual value 10 14 ohms/cm), the ultra-thin film 4
Adjacent terminals 3 do not conduct through each other.

以上の如くこの考案は半導体デイバイス1その
ものに帯電防止処理を施し、しかもこの帯電防止
処理が半導体デイバイス1の外表面にわたつて均
一かつ連続した極薄膜4を形成せしめて、他物と
の接触によつても静電気を生じさせないように
し、持続性のある帯電防止効果を有して静電破壊
及び機器へ組込んだ際の静電気による誤動作等の
発生をなくしたものである。
As described above, this invention applies antistatic treatment to the semiconductor device 1 itself, and this antistatic treatment forms a uniform and continuous ultra-thin film 4 over the outer surface of the semiconductor device 1, preventing it from coming into contact with other objects. It does not generate static electricity even when it is damaged, has a long-lasting antistatic effect, and eliminates electrostatic damage and malfunctions caused by static electricity when incorporated into equipment.

【図面の簡単な説明】[Brief explanation of the drawing]

図はこの考案の実施例を示し、第1図はこの考
案の半導体デイバイス、第2図この考案の断面
図、第3図はこの考案の本体の一部拡大断面図で
ある。 なお図中1は半導体デイバイス、2は本体、3
は端子、4は極薄膜である。
The drawings show an embodiment of this invention; FIG. 1 is a semiconductor device of this invention, FIG. 2 is a sectional view of this invention, and FIG. 3 is a partially enlarged sectional view of the main body of this invention. In the figure, 1 is the semiconductor device, 2 is the main body, and 3 is the semiconductor device.
is a terminal, and 4 is an extremely thin film.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 極く少量の帯電防止剤を含む薄い濃度の水溶液
又は水分散液の表面張力を、フツ素系界面活性剤
により30dyne/cm25℃以下にしたものを適宜の
方法で煙霧状にし、このエアロゾルの粒径5μ以
下に選択したものを半導体デイバイスの本体及び
各端子の外表面に付着させて、帯電防止剤から成
る均一かつ連続した極薄膜を該外表面に形成せし
めたことを特徴とする帯電防止処理を施した半導
体デイバイス。
A dilute aqueous solution or aqueous dispersion containing a very small amount of antistatic agent has a surface tension of 30 dyne/cm25°C or less using a fluorine-containing surfactant and is made into atomized by an appropriate method, and the particles of this aerosol are An antistatic treatment characterized in that a material selected to have a diameter of 5 μm or less is adhered to the outer surface of the main body and each terminal of a semiconductor device to form a uniform and continuous ultra-thin film made of an antistatic agent on the outer surface. Semiconductor device with
JP18310281U 1981-08-10 1981-12-09 Semiconductor devices with antistatic treatment Granted JPS5887348U (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP18310281U JPS5887348U (en) 1981-12-09 1981-12-09 Semiconductor devices with antistatic treatment
EP82304114A EP0080790A3 (en) 1981-08-10 1982-08-04 Method and apparatus for forming an extremely thin film on the surface of an object
US06/412,988 US4605574A (en) 1981-09-14 1982-08-30 Method and apparatus for forming an extremely thin film on the surface of an object
US06/745,876 US4656963A (en) 1981-09-14 1985-06-18 Method and apparatus for forming an extremely thin film on the surface of an object

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18310281U JPS5887348U (en) 1981-12-09 1981-12-09 Semiconductor devices with antistatic treatment

Publications (2)

Publication Number Publication Date
JPS5887348U JPS5887348U (en) 1983-06-14
JPS62193Y2 true JPS62193Y2 (en) 1987-01-07

Family

ID=29982064

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18310281U Granted JPS5887348U (en) 1981-08-10 1981-12-09 Semiconductor devices with antistatic treatment

Country Status (1)

Country Link
JP (1) JPS5887348U (en)

Also Published As

Publication number Publication date
JPS5887348U (en) 1983-06-14

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