JPS62199019A - Wafer treatment device - Google Patents
Wafer treatment deviceInfo
- Publication number
- JPS62199019A JPS62199019A JP4039186A JP4039186A JPS62199019A JP S62199019 A JPS62199019 A JP S62199019A JP 4039186 A JP4039186 A JP 4039186A JP 4039186 A JP4039186 A JP 4039186A JP S62199019 A JPS62199019 A JP S62199019A
- Authority
- JP
- Japan
- Prior art keywords
- gas supply
- pitch circle
- radius
- upper electrode
- circumference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000000126 substance Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 239000007789 gas Substances 0.000 description 55
- 235000012431 wafers Nutrition 0.000 description 28
- 238000005530 etching Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 7
- 239000011148 porous material Substances 0.000 description 7
- 239000012495 reaction gas Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はウェハ処理装置に係り、特に平行平板方式を用
いたドライエツチング装置、CVD装置等における反応
ガス供給装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a wafer processing apparatus, and particularly to a reaction gas supply apparatus in a dry etching apparatus, a CVD apparatus, etc. using a parallel plate method.
従来、ウェハ処理装置として、例えばドライエツチング
装置においては、加工基板(以後、ウェハと称する)の
微細・ぐターンを実現する為に、異方性エツチングが行
える平行平板方式が主流となってきている。Conventionally, in wafer processing equipment such as dry etching equipment, parallel plate methods that allow anisotropic etching have become mainstream in order to realize fine patterns on processed substrates (hereinafter referred to as wafers). .
以下、第5図に基き従来のドライエツチング装置の反応
ガス供給装置について説明する。同図において、1は反
応室であシ、この反応室1の上面に設けられているガス
導入口2から反応ガス(以後、ガスと略称する)3が定
圧室4を介し、内部へと導入される。5はタライオポン
グ等の排気手段(図示せず)により反応室1内を所定圧
にして排気する為のガス排出口であり、反応室1底面の
周縁部の所定個所に設けられている。また反応室1内に
は、多数のガス供給孔(または多孔質材)7が設けられ
た上部電極6及びウェハ9を載置した下部電極8が上下
位置に夫々対向して配設されている。Hereinafter, a conventional reaction gas supply device for a dry etching apparatus will be explained with reference to FIG. In the figure, 1 is a reaction chamber, and a reaction gas (hereinafter referred to as gas) 3 is introduced into the interior through a constant pressure chamber 4 from a gas inlet 2 provided on the top surface of the reaction chamber 1. be done. A gas exhaust port 5 is provided at a predetermined location on the periphery of the bottom surface of the reaction chamber 1 for exhausting the inside of the reaction chamber 1 to a predetermined pressure by means of an evacuation means (not shown) such as a Taliopong. Further, in the reaction chamber 1, an upper electrode 6 provided with a large number of gas supply holes (or porous material) 7 and a lower electrode 8 on which a wafer 9 is placed are arranged facing each other in the upper and lower positions, respectively. .
そしてウェハ9の加工の際には、ガス導入口2からガス
3が一担定圧室4に導入され、その後一定の所定圧を以
ってガス供給孔7を通る。この為、同図に示す如きガス
流を以って、ガス3がウェハ9表面に一様に供給される
。またウェハ9との反応後のガス3aは、ガス排出口5
を通って外部へと排出される。When processing the wafer 9, gas 3 is introduced from the gas inlet 2 into the constant pressure chamber 4, and then passes through the gas supply hole 7 with a constant predetermined pressure. Therefore, the gas 3 is uniformly supplied to the surface of the wafer 9 with the gas flow shown in the figure. Further, the gas 3a after the reaction with the wafer 9 is discharged from the gas exhaust port 5.
is discharged to the outside through the
しかしながら、上記従来例においては、定圧室4に一担
導入されたガス3は、一様く形成されたガス供給口また
は多孔質材7を通ってウェハ9へ供給される為、第5図
に示す如く外周部に行く程、ガスの流量が多くなりエツ
チング速度にばらつきが生ずるという問題がある。第6
図はこの様子を示すプラズマエツチングのエツチング特
性の代表例であシ、主な加工条件は、反応ガス; SF
a 、反応ガス圧力; 0.2Torr 、つx ハ;
St + Sin Na r下部電極温度;30’C
,RF比出力 300Wテある。同図からも明らかな様
に、ウェハ9の外周部は中心部に比べ10%程度エツチ
ング速度が大きくなっている。However, in the above-mentioned conventional example, the gas 3 introduced into the constant pressure chamber 4 is supplied to the wafer 9 through the uniformly formed gas supply port or the porous material 7. As shown, there is a problem in that the closer to the outer periphery the gas flow rate increases, causing variations in the etching rate. 6th
The figure is a typical example of the etching characteristics of plasma etching showing this situation, and the main processing conditions are: reactive gas; SF
a, reaction gas pressure; 0.2 Torr, x c;
St + Sin Na r lower electrode temperature; 30'C
, RF specific output is 300W. As is clear from the figure, the etching rate at the outer periphery of the wafer 9 is approximately 10% higher than at the center.
上記構成の反応ガス供給装置を用いたCVD装置の場合
について言えば、ウェハの外周部でCVD膜の成膜速度
が大きくなる。In the case of a CVD apparatus using the reaction gas supply device having the above configuration, the deposition rate of the CVD film increases at the outer periphery of the wafer.
従って本発明は、以上述べたウェハに供給されるガス流
量の不均一性に起因し、ドライエツチング、CVD膜形
成等のウェハ処理を均一に行うことが困難であるという
問題を解消した、ウェハ処理装置を提供することを目的
とする。Therefore, the present invention provides a wafer processing method that solves the problem that it is difficult to uniformly perform wafer processing such as dry etching and CVD film formation due to the non-uniformity of the gas flow rate supplied to the wafer. The purpose is to provide equipment.
本発明に係るウェハ処理装置は、ウェハの半径ri(i
=1.2.3・・・)の各円周上でのガス流速Wr i
、即ちウェハの半径riの円内での全ガス供給i
量Qri = R’1:、、nR(lR=輩、nRaR
” (nu ;上部電極の中心からR番目のピッチ円周
上のガス供給孔の孔数、qn:ガス供給孔からのガス供
給量、dR;ガス供給孔の孔径、C;係数)をHX2π
ri (H;ウェハと上部電極間の距離、ri:上部電
極の中心からi番目のピッチ円の半径)で除した量が、
Wrt = Wrt =たすようにピッチ円半径ri、
半径riのピッチ円周上の孔数ni及び孔径di t−
、定めた多数のガス供給孔を、全体として・者ランスさ
せて上部電極に形成するよう構成したものである。The wafer processing apparatus according to the present invention has a wafer radius ri(i
=1.2.3...) gas flow velocity Wr i on each circumference
, that is, the total gas supply amount i within a circle with radius ri of the wafer Qri = R'1: , nR (lR = y, nRaR
” (nu: number of gas supply holes on the R-th pitch circumference from the center of the upper electrode, qn: gas supply amount from the gas supply hole, dR: hole diameter of the gas supply hole, C: coefficient) as HX2π
The amount divided by ri (H: distance between the wafer and the upper electrode, ri: radius of the i-th pitch circle from the center of the upper electrode) is
Wrt = Wrt = plus pitch circle radius ri,
Number of holes ni and hole diameter di t- on the pitch circumference with radius ri
, a large number of defined gas supply holes are formed in the upper electrode by lancing them as a whole.
〔作用〕
以上のように、本発明によれば、ウェハの半径ri(i
=1.2.3・・・)の各円周上におけるガス流速が、
Wr、 m Wr、 = ・= Wri xピッチ円半
径ri、半径riの円周上の孔数ni及び孔径diを定
めた多数のガス供給孔をバランスさせて上部電極に形成
するようにしたので、ガス供給孔を通してウェハに供給
されるガスの流速は半径方向に対し常に一定となる。[Operation] As described above, according to the present invention, the radius ri(i
The gas flow velocity on each circumference of =1.2.3...) is
Wr, m Wr, = ・= Wri x Pitch circle radius ri, the number of holes ni on the circumference of the radius ri, and the number of gas supply holes with the hole diameter di determined are formed in the upper electrode in a balanced manner. The flow rate of the gas supplied to the wafer through the gas supply hole is always constant in the radial direction.
以下、第1図ないし第4図に基き本発明の実施例を詳細
に説明する。第1図は本発明の第1の実施例の説明図で
、同図(a)において、16は上部電極、17はガス供
給孔で各ピッチ円18の円周上に4個ずつ等間隔に形成
されている。rl ”” r@は、各ピッチ円18の半
径を示している。なお、奇数番目と偶数番目のピッチ円
18の円周上の各ガス供給孔17は、相互に45°をな
す中心線上位置にあシ、全体にバランスして形成されて
いる。また同図(b)にて、12はガス導入口、13は
ガス供給孔17を含むピッチ円18の円周上に形成され
た円周溝であり、14は上部電極160表面を覆ってい
る多孔質材である。Embodiments of the present invention will be described in detail below with reference to FIGS. 1 to 4. FIG. 1 is an explanatory diagram of the first embodiment of the present invention. In FIG. 1(a), 16 is an upper electrode, and 17 is a gas supply hole, four of which are equally spaced on the circumference of each pitch circle 18. It is formed. rl "" r@ indicates the radius of each pitch circle 18. Note that the gas supply holes 17 on the circumferences of the odd-numbered and even-numbered pitch circles 18 are formed at positions on the center line that form an angle of 45 degrees with each other, and are balanced throughout. Further, in the same figure (b), 12 is a gas inlet, 13 is a circumferential groove formed on the circumference of the pitch circle 18 including the gas supply hole 17, and 14 is a groove that covers the surface of the upper electrode 160. It is a porous material.
ここにおいて、同図(a) を基にガス供給孔17の形
成されているピッチ円18の中心から1番目のピッチ円
半径ri(i=1.2.3・・・)、ぎツチ円半径ri
の円周上での孔径di及び孔数niとの関係について説
明する。この第1の実施例ではウェハ(図示せず)狭面
のガス流量を中心部から外周部へ段階的に減らす為に、
孔径di及び孔数niをdi=0.2(u)、れ=4と
夫々一定とすると共に、ピッチ円半径riを最小のピッ
チ円半径r+ (−12,5m)を基準として、数列1
,2,3,4.・・・Fnl・・・(n+=1.2.3
・・・)に従った倍数に設定している。Here, based on the same figure (a), the first pitch circle radius ri (i=1.2.3...) from the center of the pitch circle 18 where the gas supply hole 17 is formed, the pitch circle radius ri
The relationship between the hole diameter di and the number of holes ni on the circumference will be explained. In this first embodiment, in order to gradually reduce the gas flow rate on the narrow surface of the wafer (not shown) from the center to the outer periphery,
The hole diameter di and the number of holes ni are kept constant as di=0.2(u) and re=4, respectively, and the pitch circle radius ri is set to the minimum pitch circle radius r+ (-12,5 m) as a numerical sequence 1.
, 2, 3, 4. ...Fnl...(n+=1.2.3
) is set to a multiple according to
前述したように、ウェハの半径riの円内での全ガス供
給量Qri、及び半径riの円周上でのガス流速Wr
iは夫々以下のように表わされる。As mentioned above, the total gas supply amount Qri within the circle with radius ri of the wafer, and the gas flow rate Wr on the circumference of the wafer with radius ri.
Each i is expressed as follows.
Qri WC去nBdB” −(1)
式中、Hはウェハと上部電極16間の距離、Cは係数、
またlは自然数である。半径rlの円内には、ピッチ円
半径r、の円周上にて4個のガス供給孔17が形成され
ている。従って、半径r、の円内で流出するガス流量Q
r+及び半径rlの円周上でのガス流r、 (w25.
Ou+)の場合、同様にしてガス流量Qrt= C+
−8−(0,2)!とな’) 、Qrf : Qr雪+
142 、 rl :r富=1:2よF) Wr、 =
Wr、が得られ流速は等しくなる。同様にしてWrl
w Wr、 = Wr、 w −= Wr@となり、ピ
ッチ円半径riのきざみ間隔を小さくしてゆけばガス(
図示せず)の流速はウェハ全面に渡って等しくなる。上
述したピッチ円半径rl、孔径d1゜孔数n1の関係を
表1に示す。Qri WC left nBdB" - (1)
In the formula, H is the distance between the wafer and the upper electrode 16, C is the coefficient,
Also, l is a natural number. Four gas supply holes 17 are formed on the circumference of a pitch circle radius r in a circle having a radius rl. Therefore, the gas flow rate Q flowing out within a circle of radius r,
Gas flow r on the circumference of r+ and radius rl, (w25.
In the case of Ou+), the gas flow rate Qrt= C+
-8-(0,2)! Tona'), Qrf: Qr snow+
142, rl : r wealth = 1:2 yo F) Wr, =
Wr, is obtained and the flow velocities become equal. Similarly, Wrl
w Wr, = Wr, w −= Wr@, and if the pitch interval of the pitch circle radius ri is made smaller, the gas (
(not shown) is uniform over the entire wafer surface. Table 1 shows the relationship among the pitch circle radius rl, the hole diameter d1°, and the number of holes n1.
表1
またガス導入口12から導入されるガスは、ガス供給孔
17を介して円周溝13及び多孔質材14を通ることに
よって円周方向に展開され、これにより円周方向におけ
るガス流速の均一性も十分維持される(同図(b)参照
)。Table 1 Furthermore, the gas introduced from the gas inlet 12 is expanded in the circumferential direction by passing through the circumferential groove 13 and the porous material 14 via the gas supply hole 17, thereby increasing the gas flow velocity in the circumferential direction. Uniformity is also maintained sufficiently (see figure (b)).
第2図は上記構成の反応ガス供給装置を用い、前述した
従来例の場合と全く同一のエツチング条件で、ウェハ上
に形成されたシリコン窒化膜(Sls Nm )にプラ
ズマエツチングを施した時のエツチング特性を示すもの
である。同図から明らかなように、エツチング速度はウ
ェハ内の位置に依存せず一定でらることがわかる。Figure 2 shows plasma etching of a silicon nitride film (SlsNm) formed on a wafer using the reaction gas supply device with the above configuration and under the same etching conditions as in the conventional example described above. It shows the characteristics. As is clear from the figure, the etching rate remains constant regardless of the position within the wafer.
次に第3図に基き、第2の実施例を説明する。Next, a second embodiment will be explained based on FIG.
この第2の実施例において、ガス供給孔17は最小のピ
ッチ円半径r4、ピッチ円半径r1の円周上の孔径山及
び孔数n、を基準として、各ぎツチ内半径rlは数列1
,2,3,4.・・・、n、・・・に従った倍数とし、
孔数niは数列112’ + 221231 ・・・1
2n−1,・・・に、また同じく孔径diは数列1,1
7ハ7゜1/2 、1ρ、・・・、1/デ、・・・(n
冨1,2.3・・・)に夫々従った倍数として設定しで
ある。また、これらガス供給孔17は各ピッチ円18の
円周上においては等間隔に、しかも全体としてバランス
した位置に形成されている。In this second embodiment, the gas supply hole 17 has a minimum pitch circle radius r4, a hole diameter peak on the circumference of the pitch circle radius r1, and the number n of holes as a reference, and the inner radius rl of each joint has a number sequence 1.
, 2, 3, 4. It is a multiple according to..., n,...,
The number of holes ni is the sequence 112' + 221231...1
2n-1,..., and similarly the pore diameter di is the number sequence 1,1
7ha7゜1/2, 1ρ,..., 1/de,...(n
The values are set as multiples according to the respective values (1, 2, 3, etc.). Further, these gas supply holes 17 are formed at equal intervals on the circumference of each pitch circle 18 and at positions that are balanced as a whole.
このように、ガス供給孔17の孔数niをピッチ円半径
riの倍率に従って累乗的に増加すると共に、孔径di
を孔数niの平方根に逆比例して減少させることにより
、円周方向におけるガスの流速を一層均一化することが
できる。嵌2は、上述したピッチ円半径rt、孔径di
及び孔数n1の関係を示したものである。In this way, the number ni of the gas supply holes 17 is increased to a power according to the multiplier of the pitch circle radius ri, and the hole diameter di
By decreasing in inverse proportion to the square root of the number of holes ni, the gas flow velocity in the circumferential direction can be made more uniform. The fit 2 has the above-mentioned pitch circle radius rt and hole diameter di.
The relationship between the number of holes and the number of holes n1 is shown.
表2 更に第4図を基に、第3の実施例を説明する。Table 2 Further, a third embodiment will be described based on FIG. 4.
この実施例の場合には、加工工数を減らすと共に円周方
向のガス流速の均一性を向上させる為に、孔径diは全
て一定(0,50)とし、各ピッチ円18の円周上の孔
数niはピッチ円半径riの円周上での孔数n1(=3
)を基準として、数列1 、2 、22゜23、・・・
I 2n−11・・・に従った倍数とし、また各ピッチ
円半径riも同様に最小のピッチ円半径r+ (=12
.5rut ) t−基準とし、数列1 、3 、7
、15 、・、 2n−1゜・・・、1.2.3・・・
)に従った倍数とするように設定しである。また、これ
らガス供給孔17は各ピッチ円1Bの円周上にては等間
隔に、しかも全体にバランスする位置に形成されている
。表3は上記第3の実施例でのピッチ円半径ri、孔径
di及び孔数niをまとめたものでおる。In the case of this embodiment, in order to reduce the number of processing steps and improve the uniformity of the gas flow velocity in the circumferential direction, the hole diameters di are all constant (0, 50), and the holes on the circumference of each pitch circle 18 are The number ni is the number of holes n1 (=3
) as a reference, the sequence 1, 2, 22゜23,...
It is a multiple according to I 2n-11..., and each pitch circle radius ri is similarly the minimum pitch circle radius r+ (=12
.. 5rut) t-based, sequence 1, 3, 7
, 15 ,..., 2n-1゜..., 1.2.3...
). Further, these gas supply holes 17 are formed at equal intervals on the circumference of each pitch circle 1B, and at positions that are balanced overall. Table 3 summarizes the pitch circle radius ri, hole diameter di, and number of holes ni in the third embodiment.
表3
なお、第1の実施例で述べた円113及び多孔質材14
は、第2及び第3の実施例においても同様に適用できる
ことは勿論である。Table 3 In addition, the circle 113 and the porous material 14 described in the first example
Of course, this can be similarly applied to the second and third embodiments.
ま九、上記各実施例の反応ガス供給装置は、グラズマエ
ッチング装置等のドライエツチング装置に適用した場合
について述べているが、反応ガス供給のもとにウェハ上
に反応生成膜を形成するCVD装置にも同様にして適用
することができる。(9) Although the reactive gas supply device of each of the above embodiments is applied to a dry etching device such as a glazma etching device, it is not applicable to CVD in which a reaction product film is formed on a wafer by supplying a reactive gas. It can be similarly applied to devices.
以上詳細に説明したように、本発明によれば、クエへ表
面に供給される反応ガスのガス流速が一定となるように
、平行平板式のドライエツチング装置、CVD装置等の
ウェハ処理装置の上部電極に、ピッチ円半径ri、ピッ
チ円半径riの円周上での孔径di及び孔数niを定め
た多数のガス供給孔を全体にバランスさせて形成する構
成としている。As described above in detail, according to the present invention, the upper part of a wafer processing apparatus such as a parallel plate type dry etching apparatus or CVD apparatus is The electrode is configured to have a pitch circle radius ri, a hole diameter di on the circumference of the pitch circle radius ri, and a large number of gas supply holes having a defined hole number ni in a balanced manner as a whole.
従ってドライエツチング、CVD膜形成等のウェハ処理
を高い均一性を以って施すことができるという効果があ
る。Therefore, there is an effect that wafer processing such as dry etching and CVD film formation can be performed with high uniformity.
第1図は本発明の第1の実施例の説明図、第2図は同第
1の実施例でのエツチング特性図、第3図は同第2の実
施例の説明図、第4図は同第3の実施例の説明図、第5
図は従来例の説明図、また第6図は同従来例でのエツチ
ング特性図である。
12・・・ガス導入口、13・・・円周溝、14・・・
多孔質材、16・・・上部電極、17・・・ガス供給孔
、18・・・ピッチ円。
壽 2 @
茎 3 図
第 4 嬌
第 5 図Fig. 1 is an explanatory diagram of the first embodiment of the present invention, Fig. 2 is an etching characteristic diagram of the first embodiment, Fig. 3 is an explanatory diagram of the second embodiment, and Fig. 4 is an explanatory diagram of the second embodiment. Explanatory diagram of the third embodiment, fifth
The figure is an explanatory diagram of a conventional example, and FIG. 6 is an etching characteristic diagram of the conventional example. 12... Gas inlet, 13... Circumferential groove, 14...
Porous material, 16... Upper electrode, 17... Gas supply hole, 18... Pitch circle. Ju 2 @ Stalk 3 Figure 4 Figure 5
Claims (1)
スを供給するガス供給孔を有する平行平板式のウェハ処
理装置において、上記加工基板と上記上部電極間距離を
H、該上部電極にて中心からi番目のピッチ円の半径を
ri(i=1、2、3・・・)、ピッチ円半径riの円
周上の上記ガス供給孔の孔数及び孔径を夫々ni及びd
i、係数をCとする時、上記加工基板の半径riの円周
上でのガス流速Wriが、▲数式、化学式、表等があり
ます▼ なる関係式を満たすよう、上記ri、ni及びdiを定
めた上記ガス供給孔を上記上部電極の全体としてバラン
スした位置に形成する構成とした事を特徴とするウェハ
処理装置。(2)上記ガス供給孔は、上記ピッチ円の円
周上の孔径di及び孔数niを一定とすると共に、上記
ピッチ円半径riを、r_1を基準として数列1、2、
3、4、・・・、n、・・・(n=1、2、3・・・)
に従つた倍数に設定して形成した事を特徴とする特許請
求の範囲第1項記載のウェハ処理装置。 (3)上記ガス供給孔は、上記ピッチ円半径riをr_
1、を基準として数列1、2、3、4、・・・、n、・
・・(n=1、2、3・・・ )に従つた倍数に設定す
ると共に、上記ピッチ円の円周上の孔数ni及び孔径d
iを、夫々n_1及びd_1を基準として数列1、2^
1、2^2、2^3、・・・、2^n^−^1、・・・
及び数列1、1/√2、1/2、1/√2^3、・・・
、1/√2^n^−^1、・・・(n=1、2、3・・
・ )に夫々従つた倍数に設定して形成した事を特徴と
する特許請求の範囲第1項記載のウェハ処理装置。 (4)上記ガス供給孔は、上記ピッチ円の円周上の孔径
diを一定とすると共に、上記ピッチ円半径ri及び孔
数niを、夫々にr_1及びn_1を基準として数列1
、2^1、2^2、2^3、・・・、2^n^−^1、
・・・及び数列1、3、7、15、・・・、2^n−1
、・・・(n=1、2、3・・・)に夫々従つた倍数に
設定して形成した事を特徴とする特許請求の範囲第1項
記載のウェハ処理装置。[Scope of Claims] (1) In a parallel plate type wafer processing apparatus having a gas supply hole for supplying a reactive gas to an upper electrode facing the arrangement position of the processed substrate, the distance between the processed substrate and the upper electrode is set to H. , the radius of the i-th pitch circle from the center in the upper electrode is ri (i=1, 2, 3...), and the number and diameter of the gas supply holes on the circumference of the pitch circle radius ri are respectively ni and d
When i and the coefficient are C, the gas flow velocity Wri on the circumference of the processed substrate with radius ri is ▲There are mathematical formulas, chemical formulas, tables, etc.▼ The above ri, ni and di are set to satisfy the following relational expression. A wafer processing apparatus characterized in that the predetermined gas supply holes are formed at positions that are balanced as a whole of the upper electrode. (2) The gas supply holes have a constant hole diameter di and a constant number of holes ni on the circumference of the pitch circle, and the pitch circle radius ri is set in the numerical sequence 1, 2, with r_1 as a reference.
3, 4,..., n,... (n=1, 2, 3...)
The wafer processing apparatus according to claim 1, characterized in that the wafer processing apparatus is formed by setting a multiple according to the following. (3) The gas supply hole has the pitch circle radius ri set to r_
Based on 1, the sequence 1, 2, 3, 4, ..., n, ...
...(n=1, 2, 3...), and the number of holes ni and the hole diameter d on the circumference of the pitch circle.
Let i be the sequence 1, 2^ with n_1 and d_1 as standards, respectively.
1, 2^2, 2^3,..., 2^n^-^1,...
and sequence 1, 1/√2, 1/2, 1/√2^3,...
, 1/√2^n^-^1,... (n=1, 2, 3...
The wafer processing apparatus according to claim 1, characterized in that the wafer processing apparatus is formed by setting multiples according to . (4) The gas supply hole has a constant hole diameter di on the circumference of the pitch circle, and the pitch circle radius ri and the number of holes ni are arranged in a numerical sequence based on r_1 and n_1, respectively.
, 2^1, 2^2, 2^3, ..., 2^n^-^1,
... and the sequence 1, 3, 7, 15, ..., 2^n-1
, . . . (n=1, 2, 3, . . . ), respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4039186A JPS62199019A (en) | 1986-02-27 | 1986-02-27 | Wafer treatment device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4039186A JPS62199019A (en) | 1986-02-27 | 1986-02-27 | Wafer treatment device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62199019A true JPS62199019A (en) | 1987-09-02 |
Family
ID=12579357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4039186A Pending JPS62199019A (en) | 1986-02-27 | 1986-02-27 | Wafer treatment device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62199019A (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5031571A (en) * | 1988-02-01 | 1991-07-16 | Mitsui Toatsu Chemicals, Inc. | Apparatus for forming a thin film on a substrate |
| US6402848B1 (en) * | 1999-04-23 | 2002-06-11 | Tokyo Electron Limited | Single-substrate-treating apparatus for semiconductor processing system |
| US6767795B2 (en) | 2002-01-17 | 2004-07-27 | Micron Technology, Inc. | Highly reliable amorphous high-k gate dielectric ZrOXNY |
| US6812100B2 (en) | 2002-03-13 | 2004-11-02 | Micron Technology, Inc. | Evaporation of Y-Si-O films for medium-k dielectrics |
| US6852167B2 (en) * | 2001-03-01 | 2005-02-08 | Micron Technology, Inc. | Methods, systems, and apparatus for uniform chemical-vapor depositions |
| US6884739B2 (en) | 2002-08-15 | 2005-04-26 | Micron Technology Inc. | Lanthanide doped TiOx dielectric films by plasma oxidation |
| US6921702B2 (en) | 2002-07-30 | 2005-07-26 | Micron Technology Inc. | Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics |
| US6953730B2 (en) | 2001-12-20 | 2005-10-11 | Micron Technology, Inc. | Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics |
| US6967154B2 (en) | 2002-08-26 | 2005-11-22 | Micron Technology, Inc. | Enhanced atomic layer deposition |
| US7166509B2 (en) | 2002-06-21 | 2007-01-23 | Micron Technology, Inc. | Write once read only memory with large work function floating gates |
| WO2006020424A3 (en) * | 2004-08-02 | 2007-06-28 | Veeco Instr Inc | Multi-gas distribution injector for chemical vapor deposition reactors |
| US7351628B2 (en) | 2002-08-22 | 2008-04-01 | Micron Technology, Inc. | Atomic layer deposition of CMOS gates with variable work functions |
| US7622355B2 (en) | 2002-06-21 | 2009-11-24 | Micron Technology, Inc. | Write once read only memory employing charge trapping in insulators |
| US8921914B2 (en) | 2005-07-20 | 2014-12-30 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
| JP2017028220A (en) * | 2015-07-28 | 2017-02-02 | 三菱マテリアル株式会社 | Electrode plate for plasma processing apparatus |
-
1986
- 1986-02-27 JP JP4039186A patent/JPS62199019A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5031571A (en) * | 1988-02-01 | 1991-07-16 | Mitsui Toatsu Chemicals, Inc. | Apparatus for forming a thin film on a substrate |
| US6402848B1 (en) * | 1999-04-23 | 2002-06-11 | Tokyo Electron Limited | Single-substrate-treating apparatus for semiconductor processing system |
| US6852167B2 (en) * | 2001-03-01 | 2005-02-08 | Micron Technology, Inc. | Methods, systems, and apparatus for uniform chemical-vapor depositions |
| US6953730B2 (en) | 2001-12-20 | 2005-10-11 | Micron Technology, Inc. | Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics |
| US6767795B2 (en) | 2002-01-17 | 2004-07-27 | Micron Technology, Inc. | Highly reliable amorphous high-k gate dielectric ZrOXNY |
| US6812100B2 (en) | 2002-03-13 | 2004-11-02 | Micron Technology, Inc. | Evaporation of Y-Si-O films for medium-k dielectrics |
| US6930346B2 (en) | 2002-03-13 | 2005-08-16 | Micron Technology, Inc. | Evaporation of Y-Si-O films for medium-K dielectrics |
| US7166509B2 (en) | 2002-06-21 | 2007-01-23 | Micron Technology, Inc. | Write once read only memory with large work function floating gates |
| US7622355B2 (en) | 2002-06-21 | 2009-11-24 | Micron Technology, Inc. | Write once read only memory employing charge trapping in insulators |
| US6921702B2 (en) | 2002-07-30 | 2005-07-26 | Micron Technology Inc. | Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics |
| US6884739B2 (en) | 2002-08-15 | 2005-04-26 | Micron Technology Inc. | Lanthanide doped TiOx dielectric films by plasma oxidation |
| US7351628B2 (en) | 2002-08-22 | 2008-04-01 | Micron Technology, Inc. | Atomic layer deposition of CMOS gates with variable work functions |
| US6967154B2 (en) | 2002-08-26 | 2005-11-22 | Micron Technology, Inc. | Enhanced atomic layer deposition |
| WO2006020424A3 (en) * | 2004-08-02 | 2007-06-28 | Veeco Instr Inc | Multi-gas distribution injector for chemical vapor deposition reactors |
| US8921914B2 (en) | 2005-07-20 | 2014-12-30 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
| JP2017028220A (en) * | 2015-07-28 | 2017-02-02 | 三菱マテリアル株式会社 | Electrode plate for plasma processing apparatus |
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