JPS6219929A - Dma controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention Technical Field The present invention relates to a DMA control device, and more specifically, in a system for processing image data having a memory for storing image data and a CPU device. The present invention relates to an MA control device suitable for speeding up data transfer and bit shift processing.

Prior Art A conventional system for processing two-dimensional image data includes a device for inputting one image signal, a memory device for storing the image data, a device for displaying an image based on the image data, a CPU device for processing various data, etc. The input image data is displayed on the CRT screen as it is, or after reconstruction processing is performed on the input image data.

When reconstructing image data, data necessary for reconstruction is read from the memory that stores the original image data and written to the memory that stores the image data being displayed. Since most of the processing is executed on the CPU device, the system throughput is reduced.

For example, when changing a constant image being displayed to another image in units of 1-pips, the CPU device must shift the constant read image data by a specified number of bits and incorporate it into the image data being displayed. , but it uses a lot of registers inside the CPU. The processing was complicated, the software was expensive, and the processing time for data transfer was long. Also,
When accessing the memory at discontinuous addresses to read/write image data one after another, the CPU device needs to update the transfer parameters from time to time, so software other than data transfer is also installed for this purpose. Ta.

An object of the present invention is to solve such conventional problems, and to provide an image data processing system that includes a memory for storing image data and a CPU, in which constant transfer of image data and image data processing are performed according to instructions from the CPU. An object of the present invention is to provide a DMA control device capable of speeding up transfer processing and improving system throughput by shifting from P1 to P1.

Structure In order to achieve the above object, the present invention provides a DMA of the present invention.
Memory and CPU for storing image data in the control device
In a system for processing the image data, the system includes a data shift means (data shift circuit section 61) for shifting the image data by an arbitrary number of bits, and the CPU.
The apparatus is characterized by comprising block transfer means (block transfer circuit unit 60) for DMA transfer of a certain block of image data in the memory designated by the apparatus.

A detailed description will be given below based on one embodiment of the present invention.

FIG. 2 is a block diagram of an image data processing system showing an embodiment of the present invention. In the figure, 1 is an image signal input device that inputs an image signal, 2 is a source memory 211 that stores original image data, a destination memory 22 that stores image data that is being displayed, and a parameter area 2.
3 is a CPU device that controls the entire system, and 4 is a CPU device that controls the entire system.
DMA control device for MA transfer and bit shifting, 5
is an image display device that displays an image using image data. Note that each of these devices is called an address bus.

Connect using a system bus consisting of a data bus and control lines.

For example, on the display screen 51 of the image display device 5 as shown in FIG. When displaying an image that incorporates CP
This is realized by the U device 3 causing the DMA control device 4 to perform data transfer, data bit shifting, etc. That is, D.M.A.
In the operations of the first to third embodiments described later, the control device 4 transfers a data block consisting of a plurality of discontinuous data on the memory to a designated area without the intervention of the CPU device 3, and similarly transfers the data to a designated area without the intervention of the CPU device 3. Image data is bit-shifted and written into a memory device 2 without the intervention of a device 3.

First, a first embodiment of the present invention will be described with reference to FIGS. 4 to 6.

FIG. 4 is a block diagram of the DMA control device 4, FIG. 5 is a block diagram of the parameter area 23, and FIG. 6 is a processing flowchart of FIG. In FIG. 4, 11 and 14 are 110 circuits that input and output address signals, 12 is a 24-bit adder that adds the offset value (jump amount) of the offset setting circuit 13 to the source address, and 15 is a transfer end signal. a DMA circuit 17 that terminates the DMA transfer of data when receiving 'transfer end' from the generation circuit 16;
is a transfer line number setting circuit that sets the number of transfer lines. Note that the number of transfer lines is rr N # lines shown in FIG.

The DMA circuit 15 of the DMA control device 4 is configured so that the CPU device 3 controls the fifth parameter area 23 on the system memory.
As shown in the figure, there is a ``source address'' to the source memory 21, a ``destination address'' to the destination memory 22, and one line of transfer.
By 1-count l-' is set in 24 bits, and then, as an initial setting, 'transfer line number' (memory block number 2N) is input to the transfer line number setting circuit 17, and 'offset value' is input to the offset setting circuit 13. ' (address value for one line) and then receives the '5TART command' to be sent, the following data transfer is performed.

That is, the DMA circuit 15 first reads the parameter area 23.
After reading each parameter of and storing it in internal register,
The data corresponding to the byte count is read from the source memory 21 at the source address of the parameter (i.e., the fixed position 52 of the image in FIG. Write to the memory 22 (step 1o1). Note that since the data amount for (1 transfer line x 1 line) is set in the byte counter, the DMA circuit 15 transfers one line of the two-dimensional transfer area 52.

Further, this data transfer will be referred to as 'DMA1 transfer' hereinafter.

Subsequently, the DMA circuit 15 updates both address values in the parameter area 23 in order to perform the primary DMA1 transfer of one line. That is, first, N-N on the system memory
+4 address data (source address) to 170 circuits 11
, and the 24-bit adder 12 adds the offset value of the offset setting circuit 13 to the transferred value.
○After being set in the circuit 14, the added value is written again to address N-N+4 on the system memory (step 103).
). Note that this data transfer is hereinafter referred to as 'DMA2 transfer'.

By repeating the above transfer operation, data is read with the updated source address and written with the similarly updated destination address (DMA transfer), all N lines are DMA transferred and the process is completed. do(
Step 102). In addition, in order to finish the transfer process,
The transfer end signal generation circuit 16 is connected to the transfer line number setting circuit 1.
The number of transfer lines of 7 is decremented every time one line is transferred, and when it becomes II Ogg, the DMA circuit 1
5, outputs a 'transfer end signal' to end the DMA transfer.

In this way, data for the number of transfer lines is transferred while updating the initially set parameters, so a certain amount of image data (i.e., data blocks) that continues in a discontinuous state is transferred.
Data transfer can be performed using only the DMA control device 4. As a result, the CPU Wt3 sets the transfer parameters, offset values, etc., and is not concerned with anything after that.
This improves the throughput of U and enables multitasking as a system. Further, the present DMA control device 4 is particularly effective for transferring two-dimensional data in an image memory.

Next, a second embodiment of the present invention is shown in FIGS. 7 and 8(a) to 8.
This is explained by (i).

FIG. 7 is a block diagram of the DMA control device 4, and FIG. 8(a) to (
i) is a diagram for explaining the operation of FIG. 7; In FIG. 7, 31 and 34 are latch circuits that temporarily store source data, 32 and 35 are shift register circuits that bit-shift source data to the right or left according to instructions from shift control circuits 33 and 36, respectively, and 37 is a destination.・OR circuit that generates data, 38.39
40 is a buffer circuit that temporarily stores 8-bit data on the MSB and LSB sides, 40 is a DMA @ path that performs bit shifting and read/write processing of data by the method described later, and 41 is an MRDC that distributes read data to a destination. The distribution is to the circuit, and 42 is the MW that distributes the source of the write data.
TC distribution is a circuit.

Now, as shown in FIG. 3, on the display screen 51 of the image display unit 5, for example, when displaying a constant 54 of another image in place of a constant 53 of the currently displayed image, the DMA circuit 40 of the DMA control device 4 The image data corresponding to constant 53 (hereinafter referred to as destination data), the image data corresponding to constant 54 (hereinafter referred to as source data), the number of transfer bytes, and the number of shift bits are instructed by the CPU device 3. Then, the MRDC distribution first sends out a memory read command (Is read signal) from the circuit 41, and latches the source data (So=37) shown in FIG. 8(a) instructed from the source memory 21. The signal is read out to the circuit 31, and the shift control circuit 33 shifts the 8-bit output of the latch circuit 31 to the MSB side by 3 bits to the right as shown in FIG. 8(b), and sets the result in the shift register circuit 32.

Note that the CPU device 3 starts operating when a certain bit (in one byte) of destination data and source data is designated by a position pointing device such as a mouse (not shown).

After that, the shift register circuits 32 and 35 are connected to the OR circuit 37.
After ORing both 16-bit outputs to create the byte shown in FIG. 8(c), the MWTC distribution causes the circuit 42 to send a memory write command (IS write signal),
The MSB side 8 bits from the R circuit 37 are transferred to the buffer circuit 38.
The data is written to the designated area of the destination memory 22 through. Note that at this point, the 16-bit output from the shift register circuit 35 is a11'"0". Also, the first destination data is O
Since it is on the MSB side of the 16-bit output of the R circuit 37,
1st, the data buffer circuit 38 is enabled by a write signal. As a result, the first byte (SO”
The data transfer including the shift in S7) is completed.

Subsequently, the DMA circuit 40 causes the circuit 41 to send out a memory read command (2nd read signal) for MRDC distribution in the same manner as described above, and reads the next (2nd byte) 8th byte instructed by the source memory 21. The source data (8
8 to 515) to the latch circuit 34, and the 8-bit output of the latch circuit 34 to the shift control circuit 36.
As shown in FIG. 3(e), the data is shifted 3 bits to the right on the LSB side and set in the shift register circuit 35.

After that, similarly, the OR circuit 37 is connected to the shift register circuit 32.
After ORing the surface outputs of 35 to create the byte shown in FIG. 8(f), MWTC distribution is performed by memory write/
A command (2nd write signal) is sent, and the LSB side 8 bits from the OR circuit 37 are written into the next designated area of the destination memory 22 as destination data through the buffer circuit 39.

Note that at this point, 16 from the shift register circuit 32
The output from bit i has the contents (So=87) shown in FIG. The data buffer circuit 39 is enabled.

The operation of the first byte above is the third byte (816-523)
Then, the operation of the second byte is changed to the fourth byte (S24 to S53).
1), repeat in sequence, i.e.,
After alternating between the 1st and 2nd read signals, read out the source data, shift the bits, and perform ORing, 1. s
The t and /2st write signals are also alternately switched and written to the destination memory 22. This operation is performed by shifting and transferring all the data of the specified number of bytes from the CPU device 3.

In this way, the source data is read out and shifted by the shift register circuits 32 and 35, and the logical OR data is written again to the destination memory 22, so image reconstruction can be executed only by the DMA control device 4. is possible. As a result, the transfer time can be greatly shortened compared to data transfer using the conventional CPU device 3, and the throughput of the present system can be improved.

Next, a third embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a block diagram of the DMA control device 4. As shown in FIG. In the figure, 60 is a block transfer circuit section having the same function as the circuit shown in FIG. 4 described above, 61 is a data shift circuit section having the same function as the circuit shown in FIG. 7 described above, and 62 is a circuit block shown in FIG. 7. A data shift circuit 63 is a DMA having both functions of the above-mentioned DMA circuits 15 and 40.
It is a circuit.

By combining the block transfer function according to the first embodiment described above and the data shift function according to the second embodiment described above, the DMA control device 4 transfers two-dimensional image data in units of bits rather than bytes or word boundaries. It becomes possible to perform DMA transfer (image reconstruction).

To realize the above, the DMA circuit 63 of the DMA control device 4
is stored in the source memory 2 according to the contents and offset values of the parameter area 23 initialized by the CPU device 3.
If you want to read the image data at the source address from 1 and shift the bits of that (image) data, shift the specified number of bits in the data shift circuit 62 (left/right shift possible), and then shift the shifted data to the destination. write to the destination memory 22 using the destination address (see DMAI transfer in the second embodiment and the first embodiment).

In this operation, the DMA circuit 63 transfers (1 transfer line x 1 line) worth of data to the transfer area in real time,
After the transfer is complete, update the parameters (source address, destination address) necessary for the transfer (
(See DMA2 transfer in the first embodiment). After updating the parameters, data transfer for the second line is performed in the same manner as for the first line, all N lines are DMA transferred, and the process ends.

In addition.

At the end of the DMA transfer, the transfer end signal generation circuit 16 decrements the number of transfer lines for each line transfer, and the transfer end signal generation circuit 16 decrements the number of transfer lines to 90''.
This is done by sending a 'transfer end signal' to the DMA circuit 63 when the transfer end signal is reached (see the first embodiment).

In this way, the source data read out by the data shift circuit section 62 is bit shifted L-L, and one block transfer circuit section 60 is moved from a certain area (two-dimensional area) of the image memory corresponding to the CRT screen to another area. Therefore, the DMA control device 4 receiving instructions from the CPU device 3 can transfer the image data and perform bit shifting.

This makes it possible to easily perform pixel-by-pixel reconstruction processing compatible with a CRT screen, and to move images with bit-by-bit resolution. In addition, the DMA control device 4 automatically performs data transfer and bit shifting, and
It is possible to perform parallel processing with the U device 3 and build a system with high throughput.

Effects As explained above, according to the present invention, in an image data processing system having a memory for storing one image data and a CPU device, D
Since the MA control device causes the data shift circuit section to bit shift the source data and causes the block transfer circuit section to DMA transfer a certain portion of the image data, data transfer and bit shift processing become faster, and the throughput of this system improves. .

[Brief explanation of drawings]

1, 4, and 7 are configuration diagrams of a DMA control device showing third, first, and second embodiments of the present invention, respectively, and FIG. 2 is a configuration diagram of an image data processing system according to the present invention. 3 is a diagram showing the display screen, FIG. 5 is a configuration diagram of the parameter area, FIG. 6 is the processing flowchart of FIG. 4, and FIGS. 8(a) to (i) are the diagrams of FIG. FIG. 3 is a diagram for explaining the operation. image signal input device, 2: memory device, 3: CPU device, 4: DMA control device, 5: image display device, 11, 14
: I10 circuit, 12: 24-bit adder, 13: Offset setting circuit, 15, 40.63: DMA circuit, 16 two-transfer end signal generation circuit, 17: Transfer line number setting circuit,
21: Source memory, 22: Destination memory, 23: Parameter area, 31, 34: Lasochi circuit, 32. 35: Shift register circuit, 33. 36: Shift control circuit, 37: OR circuit, 38° 39: Buffer Circuit, 41: MRDC distribution is a circuit, 42: M
WTC distribution is circuit, 51: Display screen, 52.52a, 5
3, 54: Constant image, 60 niblock transfer circuit, 6
1: Data shift circuit section, 62: Data shift circuit.

Claims (3)

[Claims] (1) In a system that includes a memory for storing image data and a CPU device and processes the image data, a data shifting means for shifting the image data by an arbitrary number of bits, and a constant value in the memory designated by the CPU device. 1. A DMA control device comprising block transfer means for DMA transfer of block image data. (2) The data shifting means includes means for bit-shifting the image data to the right or left and outputting it as 16-bit data, means for ORing the 16-bit output data, and a destination for importing the image data. 2. The DMA control device according to claim 1, further comprising means for specifying the output data of the logical sum means, and means for storing the output data of the logical sum means in the memory in 8 bits. (3) The block transfer means includes means for storing an offset value between image data in a discontinuous state, and means for determining an address of the memory based on the offset value;
2. The DMA control device according to claim 1, further comprising means for outputting a 'transfer end signal' to end the DMA transfer when a specified amount of data has been transferred.