JPS6219992Y2 - - Google Patents

Description

[Detailed Description of the Invention] <Technical Field> The present invention relates to a microprocessor system for watches that employs a ROM/RAM system.

<Prior art> Currently, in digital electronic watches, one clock function is built into an LSI using random logic, and even if an attempt is made to provide one with a different type of function, it is only realized by applying the same type of LSI. It was extremely difficult to do so. By the way, when configuring a digital clock using the ROM/RAM method, changing the function is done by simply changing the way the programs stored in the ROM are assembled, and the hardware part can be used in common even if the functions are different. Can be done. That is,
Digital electronic clocks with different functions are available at LSI.
It is possible to obtain a different model simply by changing the mask in the program section of the ROM, making circuit design extremely easy. This is a big advantage over random logic. However, this
The ROM/RAM method has the drawback of high power consumption, which has delayed its practical application.

<Purpose of the invention> In view of the above points, the present invention provides a digital electronic clock with low power consumption using the ROM/RAM method.

<Structure of the invention> The microprocessor system for a watch of the present invention is a microprocessor system for a watch that has a timekeeping means using a ROM/RAM method, and includes an oscillator that outputs a basic clock of a predetermined frequency, and an output of the oscillator. a frequency divider that divides the frequency of the basic clock and outputs a first unit time signal; a counter that outputs a second unit time signal having a maximum value; and a system clock that receives the output of the counter and intermittently outputs a system clock for each second unit time signal based on the second unit time signal. a generator;
RAM reading means for reading time data from the RAM and supplying it to the decoder in response to each system clock from the system clock generator;
a decoder that receives the time data from the reading means and the lower digit time data from the counter and converts them into display signals; a display register that receives the output of the decoder and holds the display signal; A circuit is provided that selects the output of the display register and the output of the decoder and supplies it to the display means, and the time measurement means receives the system clock of the system clock generator, thereby performing time measurement calculations. It is characterized by a configuration that performs operations.

<Operation of the invention> The invention will be described below with reference to the drawings. FIG. 1 is a block diagram, and FIG. 2 is a time chart showing its operation.

A time measuring means 7 consisting of a program counter 1, a ROM 2, a data address register 3, a RAM 4, an arithmetic unit (ALU) 5, and an accumulator 6 is used to measure time over minutes such as month, day, hour, minute, etc., and alarm coincidence. is being carried out. The flow process of the program is every 1 minute pulse m. A 60-second counter 10 that counts 1-second pulses S is provided as a hardware after the oscillator 8 and frequency divider 9.
is to obtain the 1-minute pulse m for this purpose,
The system clock generator 1 receives the 1-minute pulse m.
1, a system clock C corresponding to the number of steps K is generated once per minute.

Now, assuming that the frequency of system clock C is ₀ , if a system clock is always generated, ₆₀₀ system clocks are supplied per minute. On the other hand, the system described above only supplies the system clock for the number of program steps K once per minute, and if the ratio of the two is set to A, then A=K/ ₆₀₀ , and the power consumption can be reduced to this value. It can be made smaller with the ratio of A.

In each mode, the selected time measurement data is input to the display register 14 via the buffer register 12 and the segment decoder 13, and is displayed through the output terminals 19 and 20. Reading into the display register 14 is of course carried out during the generation of the system clock C mentioned above.

As described above, the system clock C is supplied to the program counter 1, ROM 2, data address register 3, RAM 4, ALU 5, accumulator 6, buffer register 12, and display register 14 every minute pulse m. As a result, a time calculation operation and a reading operation of a display signal corresponding to the calculation result into the display register 14 are performed every minute pulse.

By the way, the 60-second counter 10 provided as a hardware is capable of generating second timing data. Therefore, in addition to the clock data in the RAM 4, second clock data can also be displayed here.

The OR gate 16 also inputs second clock data to the segment decoder 13, and the second clock data is input to the segment decoder 13 every moment. When the 60 second counter 10 counts one minute, the system clock C is generated and the clock data in the minute digits and above in the RAM 4 is also input to the segment decoder 13, but at this time, the contents of the 60 second counter 10 become 0.
Since it is in the state of second timekeeping, timekeeping data can be decoded from RAM 4 without mixing with second timekeeping data. In this way, the segment decoder 13 decodes the clock data output from the RAM 4 when the one-minute pulse m occurs, and decodes the second clock data at other times.

The AND gate 17 inputs the decoder output, the inverted signal of the 1-minute pulse m, and the second display mode signal Sm, and supplies second time measurement data to the output terminal 20 via the OR gate 18 when the second display mode signal Sm is present. Note that the other input of the OR gate 18 is supplied with the signal from the display register 14 as described above, but when the second display mode is selected, no signal is supplied, and at this time, the output terminal Seconds are displayed through 20. Also, 0
When the time is seconds, the inverted signal prevents the decoder output on the RAM 4 side from being directly supplied to the output terminal 20.

In the above explanation, the flow processing of the program is performed every minute, but it is also possible to generate the system clock every hour or more and perform flow processing.
Of course, in these cases, the hardware design will also be slightly different. Note that the seconds display is not necessarily necessary; OR gate 16, AND gate 1
7 and the OR gate 18, etc., may be omitted without any problem. However, even in this case, if seconds display etc. is desired, the counter for generating the system clock can be used in common, and the decoder can also decode this time measurement data outside of the system clock generation period. This is useful because it has the advantage of being able to provide an electronic timepiece with a simple configuration and more displays.

<Effects of the invention> As described above, according to the invention, in the ROM/RAM system, the system clock is generated once every time of the lowest time digit to be processed by the flow, and the system clock is generated once for each lowest time of the time digit to be processed by the flow. We can provide watches. In addition, this device uses a counter and decoder that generates the system clock in common to display time in lower digits, so it is possible to increase the number of time displays without complicating the structure. This has the advantage of being extremely useful.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a time chart showing the operation of FIG. 1. 1...Program counter, 2...ROM, 3
...Data address register, 4...RAM, 5
...Arithmetic unit, 6...Accumulator, 7
...Time measuring means, 8...Oscillator, 9...Frequency divider, 1
0...60 seconds counter, 11...System clock generator, 12...Buffer register, 13...Segment decoder, 14...Display register, 1
6...or gate, 17...and gate, 18
...OR gate, 19,20...output terminal.

Claims (1)

[Scope of utility model registration request] A clock microprocessor system having a ROM/RAM type timekeeping means includes an oscillator that outputs a basic clock of a predetermined frequency, and a first clock that divides the basic clock based on the output of the oscillator.
a frequency divider that outputs a unit time signal; and a frequency divider that receives the output of the frequency divider, counts the first unit time signal, outputs lower digit time data, and at the same time outputs a second unit time signal of the maximum value. a system clock generator that receives the output of the counter and intermittently outputs a system clock every second unit time based on the second unit time signal; A RAM reading means that reads out time data from the RAM and supplies it to the decoder in response to each system clock; and a RAM reading means that receives the time data from the RAM reading means and the lower digit time data from the counter and converts them into a display signal. a decoder for conversion; a display register that receives the output of the decoder and holds the display signal;
a circuit for selecting the output of the display register and the output of the decoder and supplying the selected output to the display means;
A microprocessor system for a timepiece, characterized in that said timekeeping means is configured to receive a system clock from said system clock generator and thereby perform timekeeping operations.