JPS62205U - - Google Patents
Info
- Publication number
- JPS62205U JPS62205U JP8933385U JP8933385U JPS62205U JP S62205 U JPS62205 U JP S62205U JP 8933385 U JP8933385 U JP 8933385U JP 8933385 U JP8933385 U JP 8933385U JP S62205 U JPS62205 U JP S62205U
- Authority
- JP
- Japan
- Prior art keywords
- stage
- input terminal
- audio signal
- circuit
- inputted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000005070 sampling Methods 0.000 claims 3
- 230000005236 sound signal Effects 0.000 claims 3
- 238000009795 derivation Methods 0.000 claims 1
- 230000007774 longterm Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Television Signal Processing For Recording (AREA)
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
Description
第１図は本考案の一実施例を示す回路ブロツク
図、第２図は第１図の信号波形説明図をそれぞれ
示す。
７……第１Ｄタイプフリツプフロツプ、８……
第２Ｄタイプフリツプフロツプ、４……（第２）
ドロツプアウト検出回路、１１……ゲート回路。
FIG. 1 is a circuit block diagram showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram of signal waveforms in FIG. 1. 7...1st D type flip-flop, 8...
2nd D type flip-flop, 4...(2nd)
Dropout detection circuit, 11...gate circuit.
Claims (1)
録して成るビデオテープを再生し、再生ＦＭ音声
信号の長期のドロツプアウトを検出するドロツプ
アウト検出回路の検出出力に基づいて音声信号の
導出を阻止するゲートを設けて成るハイフアイＶ
ＴＲのミユート回路に於て、 ヘツド切換信号の立上りと立下りに同期してサ
ンプリングパルスを発生するサンプリングパルス
を発生するサンプリングパルス発生回路と、 従属接続されたｎ段（ｎは２以上の整数）のＤ
タイプフリツプフロツプの初段のＤ入力端子を一
方のレベルに固定し、各段のプリセツト入力端子
に前記検出出力を入力すると共に各段のクロツク
入力端子に前記サンプリングパルスを入力し、そ
の出力を前記ゲートの制御入力とするシフトレジ
スタとを、 それぞれ配して成るハイフアイＶＴＲのミユー
ト回路。[Claim for Utility Model Registration] A videotape obtained by frequency multiplexing recording of an FM audio signal onto a video track is played back, and the audio signal is detected based on the detection output of a dropout detection circuit that detects a long-term dropout of the reproduced FM audio signal. High eye V comprising a gate to prevent derivation
In the TR mute circuit, there are a sampling pulse generation circuit that generates sampling pulses in synchronization with the rise and fall of the head switching signal, and n stages (n is an integer of 2 or more) connected in cascade. D of
The D input terminal of the first stage of the type flip-flop is fixed at one level, the detection output is inputted to the preset input terminal of each stage, and the sampling pulse is inputted to the clock input terminal of each stage, and the output is A mute circuit for a high-speed VTR, comprising: a shift register serving as a control input of the gate;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8933385U JPH0445174Y2 (en) | 1985-06-13 | 1985-06-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8933385U JPH0445174Y2 (en) | 1985-06-13 | 1985-06-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62205U true JPS62205U (en) | 1987-01-06 |
| JPH0445174Y2 JPH0445174Y2 (en) | 1992-10-23 |
Family
ID=30643306
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8933385U Expired JPH0445174Y2 (en) | 1985-06-13 | 1985-06-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0445174Y2 (en) |
-
1985
- 1985-06-13 JP JP8933385U patent/JPH0445174Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0445174Y2 (en) | 1992-10-23 |
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