JPS62208664A - Manufacture of semiconductor memory - Google Patents

Abstract

PURPOSE:To improve the rate of remedy for faulty cells by a method wherein a specified fuse is exposed to an oxygen or nitrogen ion beam after the construction of a chip for the conversion of the fuse into an insulating layer. CONSTITUTION:A fuse section is provided with a first layer Al wiring 14, a SiO2 film 15 formed in plasma is attached thereto to serve as an interlayer insulating film, and then a through-hole is provided wherein a second layer Al wiring 16 is formed in the same process wherein an element section is built. Next, a PSG film 17 is formed to serve as a protecting film. After the construction of a DRAM in this way, a faulty bit is extracted and a fuse corresponding thereto is disconnected. In this process, an oxygen or nitrogen ion beam 18 is steered by magnetism or static forces and focused on the selected fuse. The beam working jointly with the heat generated in a prior ion implantation process converts the second layer Al wiring 16 into an insulating alumina layer 19. This method improves the rate of remedy for faulty cells.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor memory device, and
This invention relates to a method for repairing defective bits such as the following.

(Prior Art) In recent years, the capacity of dynamic RAMs (DRAMs) has increased dramatically, and 1M bits have even appeared. As a result of increasing capacity, it has become essential to repair defective bits due to process failures, and devices equipped with redundant circuits are also appearing. In other words, defective bits are identified through testing, the fuse group is irradiated with a laser beam to blow out the designated fuses, the defective bits are stored in the chip, and when used, the defective bits are replaced with redundant bits for operation. be.

However, lasers require a considerable amount of energy to fuse the wiring. In order to obtain this excessive energy, the laser beam diameter needs to be about 10 μm, and the alignment must be mechanically aligned, making it difficult to miniaturize the fuse part and reducing the number of redundant bits. There is a limit. In the future, as the scale increases to 4M and 16M,
This problem is even more serious.

In addition, this excessive energy damages components other than the fuse, causing leakage current and resulting in defective chips, resulting in a series of accidents.

(Problems to be Solved by the Invention) As described above, as long as a laser beam is used, there is a problem that it cannot keep up with the increase in capacity and the defective rate of chips is high.

Therefore, it is an object of the present invention to provide a highly reliable method for cutting a fuse for repairing defective bits used in a large capacity memory.

[Structure of the invention]

(Means for Solving the Problems) That is, the gist of the present invention is to irradiate a predetermined fuse with an oxygen or 9-element ion beam after manufacturing a chip to form an insulating layer on the fuse.

(Function) For example, when an oxygen ion beam is implanted into At, alumina (A
) is generated and the fuse is insulated and turned OFF.
state.

Ion beams can have an extremely small diameter compared to laser beams for fusing, and have high positional accuracy, so they are suitable for miniaturizing fuses. will no longer cause damage.

(Embodiment) FIG. 1 is a diagram showing an embodiment of the present invention, in which (a) is a plan view of a fuse portion, and (b) is a sectional view taken along line A-AI.

First, a field oxide film 12 having a thickness of about 1 μm is formed on a P-type silicon substrate 11 . Next, element formation is performed, and CV
D5iO, film 3000^, then BP8G film 7000A
cover with This is indicated by 13 (total 1 μm) in the figure. In the element portion, for example, a capacitor electrode is formed of the first M polycrystalline silicon, and a gate electrode is formed of the second layer polycrystalline silicon. In the element portion, the first layer A/= is provided as a wiring, and at this time, the kt wiring 14 is also provided in the fuse portion. After that, plasma S10! is used as an interlayer insulating film. A film 15 of 1.2 .mu.m thick is deposited, a through hole is opened, and a 0.4 .mu.m thick second layer At 16 is formed as a fuse in the same process as the element part. After that, a PSG film 17 with a thickness of 0.4
μm is formed.

After manufacturing the DRAM chip in this way, the defective bits are extracted and the corresponding fuses are cut. That is, the oxygen ion beam 18 was focused on the chip, the beam diameter was narrowed to 0.2 to 2 μm, and the oxygen ion beam 18 was deflected by electromagnetic force or electrostatic force, and irradiated onto a predetermined fuse. Accelerating voltage 340KeV, dose amount 1Xl
The temperature was set to 0"ctI.The second
The layer AL16 changed into alumina (kA, O,) l9 and became an insulating layer.

If desired, an annealing step such as furnace heating or laser annealing may be added. In any case, the amount of heat applied to the chip is smaller than in the fusing method.

In order to explain the operation of the redundant circuit, a circuit diagram of the fuse section is shown in FIG. FIG. 3 is a plan view of the chip.

So-called process defects include random bit defects and row and column defects. Therefore, row R/D (redundancy) cells 31 are arranged in the longitudinal direction of the chip, and column R/D cells 32 are arranged in the short side direction. That is, if there is a random bit defect in the core circuit, the entire row or column is operated by replacing it with a row R/D cell or a column R/D cell. Row.

Column defects can also be relieved by replacing row R/D cells and column R/D cells. In other words, only the same number of random bit defects or row and column defects as the number of R/D cell strings can be repaired.

The fuse permanently stores the row or column address where the defect exists in the chip. □The address signal consists of complementary signals AN and AN. □
That is, A, A=H, Lte@l', L, H and "Q"
means. Therefore, address designation requires fuses equal to the number of bits of the address signal x 2. And this one
Further fuse groups for the row and column R/D cell rows are provided on the chip. FIG. 3 shows a fuse region 33 for row R/D cells and a fuse circuit 3 for column R/D cells.
4 was shown. 30 is a core circuit, that is, an original memory cell array area.

In this way, one fuse group is assigned to one R/D cell column. FIG. 2 is a circuit diagram of this one hiss group. That is, for node N, fuse F and MO
A set of 8FETQl is connected.

Further, a precharge MO8FETQx is connected to the node N. The complementary signals AN, AN (N=
0, 1,...) are input. Each fuse F is AN so that the address of the defective row or column to which this R/D cell column is assigned is stored.

One side of the AN is disconnected. The node N is charged to Vcc by the precharge signal φ, and an address signal is always inputted as in the core area, and when the address signal is other than the address stored in this fuse group, the node N is discharged via the fuse. . However, when the address stored in the fuse group comes in, the node N is at "H" and the R/D signal is output. If you pay attention to Ao and Ao, here the fuse on the Ao side is blown. Ao, A
When o=“L” and “H”, no discharge path with node N occurs. At -AI . . . If the same holds true below, the R/D signal is output since it matches the storage address as described above.

When the R/D signal is output, reading or writing is performed to the corresponding R/D cell column instead of the defective memory cell column.

Now, in the previous embodiment, kA was used as the fuse. However, polycrystalline silicon may also be used.

Figure 4 is as a fuse! This is an example in which a two-layer polycrystalline silicon 41 and a first layer At14 are used as contact wiring.

Of course, the polycrystalline silicon is common to the device and is therefore doped with P or B or the like. In the CVD BP8G film 13, a fuse circuit is also opened when a contact hole is opened in the element portion. The plasma 5i01 film 15 on the first layer At is also removed on the fuse part when opening the through-hole in the element part. Therefore, the oxygen ion beam
Injected through membrane 17.

In Figure 5, the first fuse is used to increase the pitch.
A second layer of polycrystalline silicon 51 and 52 is used. The interlayer insulating film is 5VI)8i0. A membrane 53 is used. This figure shows a cross section in the direction in which the fuses are arranged. By changing the acceleration voltage during ion implantation, oxygen ions can be implanted into the first layer and second layer polycrystalline silicon with good controllability. Contact hole in element part,
When opening a through hole, use CVD + BP8 in the fuse section.
The G film 13 and the sputtered 5in2 film 15 may be removed,
Furthermore, at this time, the CVD 5iO film 53 may also be etched at the same time (FIG. 6).

In the above description, At and polycrystalline silicon are used as the fuse, but other metals or silicide films may also be used. Further, a nitrogen ion beam may be used instead of the oxygen ion beam. Further, the uniformity of ion implantation can be improved by performing multi-stage implantation by changing the acceleration voltage.

〔Effect of the invention〕

In the present invention, the fuse can be made into an insulating layer using a narrow ion beam, and in this case, the positional inconsistency can be made high by electromagnetic force or electrostatic force, and therefore it is possible to provide a significantly larger number of fuses for VD. Therefore, the repair rate of defective cells can be increased.

In addition, because it does not require excessive thermal energy such as fusing,
If the fuse circuit is also damaged, the problem of lower yield can also be improved.

Furthermore, as shown in FIG. 1, materials such as A/-, which have a high reflectance, which has been a problem with lasers, can be used without problems.

[Brief explanation of drawings]

Fig. 1 is a diagram of the fuse section explaining the embodiment, Fig. 2 is a circuit diagram showing the fuse circuit, Fig. 3 is a plan view of the chip, and Figs. It is a sectional view of an example. In the figure, ]4...first layer At14...second layer
Layer kt (fuse), 18...Oxygen ion beam. Agent Patent attorney Nori Ken Chika Yudo Kikuo Takehana (b) Figure l ■CC Pa lo/'11. N Figure 2

Claims (3)

[Claims] (1) In a method for manufacturing a semiconductor memory device in which a group of fuses for storing a defective memory area is provided on a chip and the defective memory area is operated by replacing the defective memory area with a normal memory area, a predetermined fuse is irradiated with an oxygen or nitrogen ion beam to insulate it. A method of manufacturing a semiconductor memory device, characterized in that the address of a defective memory area is memorized by cutting the fuse by layering. (2) The method for manufacturing a semiconductor memory device according to claim 1, wherein the fuse is an Al or polycrystalline silicon film. (3) The semiconductor memory device according to claim 1, characterized in that the fuses are alternately arranged in conductor films of different layers, and the acceleration voltage of the ion beam is changed depending on the layer. Production method.