JPS622093U - - Google Patents
Info
- Publication number
- JPS622093U JPS622093U JP9390085U JP9390085U JPS622093U JP S622093 U JPS622093 U JP S622093U JP 9390085 U JP9390085 U JP 9390085U JP 9390085 U JP9390085 U JP 9390085U JP S622093 U JPS622093 U JP S622093U
- Authority
- JP
- Japan
- Prior art keywords
- address
- memory
- data
- upper address
- changing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Description
第１図乃至第３図はそれぞれこの考案による設
定表示器の一例を示す接続図である。
１１：メモリ、１２：アドレス設定器、１３：
デコーダ、１４ａ，１４ｂ：表示信号、１５ａ，
１５ｂ，１６ａ，１６ｂ，２３ａ，２３ｂ，２４
ａ，２４ｂ：表示素子、１７：クロツク発生器、
２２ａ，２２ｂ，２２：駆動回路、２５：ｎ進カ
ウンタ、２６：選択用デコーダ、２７：マルチプ
レクサ。
1 to 3 are connection diagrams each showing an example of a setting display according to this invention. 11: Memory, 12: Address setter, 13:
Decoder, 14a, 14b: display signal, 15a,
15b, 16a, 16b, 23a, 23b, 24
a, 24b: display element, 17: clock generator,
22a, 22b, 22: drive circuit, 25: n-ary counter, 26: selection decoder, 27: multiplexer.
Claims (1)
と対応したアドレスを与えるアドレス設定手段と
、 上記メモリに与えられる上位アドレスを周期的
に変更する上位アドレス変更手段と、 上記メモリから読出されたデータが供給され、
そのデータを表示信号にデコードするデコーダと
、 そのデコーダの出力表示信号が供給される複数
の表示素子と、 上記上位アドレス変更手段による上記上位アド
レスの変更と同期して上記複数の表示素子の動作
を順次切替える選択動作手段とを具備する設定表
示器。[Claims for Utility Model Registration] A memory in which data to be set is stored; address setting means for assigning an address corresponding to the data to be read to a lower address of the memory; and periodically changing the upper address assigned to the memory. upper address changing means for changing the upper address; and the data read from the memory is supplied;
a decoder that decodes the data into a display signal; a plurality of display elements to which the output display signal of the decoder is supplied; and an operation of the plurality of display elements in synchronization with the change of the upper address by the upper address change means. A setting display device comprising selection operation means for sequentially switching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9390085U JPS622093U (en) | 1985-06-21 | 1985-06-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9390085U JPS622093U (en) | 1985-06-21 | 1985-06-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS622093U true JPS622093U (en) | 1987-01-08 |
Family
ID=30651991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9390085U Pending JPS622093U (en) | 1985-06-21 | 1985-06-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS622093U (en) |
-
1985
- 1985-06-21 JP JP9390085U patent/JPS622093U/ja active Pending
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