JPS6221260B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to solid-state integrated electronic circuit components, and more particularly to improvements in a substrate portion on which circuit components are mounted. Conventionally,
A printed wiring layer is provided on a substrate made of ceramic or the like, and a large number of resistors, inductive elements, capacitive elements, and active elements (transistors, diodes, etc.) are soldered to create an integrated circuit, which is then used as a unit. In this case, disk-shaped or chip-shaped capacitors must be installed one at a time.

The present invention provides multiple capacitor functions on the substrate itself by modifying the substrate portions of a solid state integrated electronic circuit, thereby simplifying the manufacturing of the integrated circuit. Further, in the present invention, the structure of the substrate section is carried out by a method suitable for mass production by lamination or printing.

Briefly, the present invention consists of alternately laminating dielectric layers and internal electrodes for a capacitor, then laminating a layer with a low dielectric constant thereon, and baking the layer to form a laminate. Lead wires and lead terminals for other circuits are provided mainly around the periphery of the fired laminate, and conductive layers and electronic circuit components made of various printed wirings are arranged and connected directly on the top surface of the laminate. Since the electronic circuit component according to the present invention constitutes one unified chip-like product as a whole, it can be placed directly on a printed circuit board,
A major feature is that the lead terminals provided on the periphery of the laminate can be directly soldered to the printed wiring on the printed circuit board of electronic equipment. Among the components of the present invention, a large number of substrates (including capacitors) can be manufactured by laminating or printing at the same time, making quality control easy, mass production, and efficiency. Efficiency is also achieved in this respect by reducing the number of steps required to assemble and complete integrated circuit components because the substrate includes capacitors.

The invention will now be explained in detail in conjunction with the drawings.

1 to 6 show the manufacturing process of the solid-state integrated electronic circuit of the present invention before the firing process, and FIGS. 7 to 10 show the steps after the firing process. In the following description, it is assumed that the dielectric layer is manufactured by a sheet method or a printing method, and the capacitor electrode is manufactured by a printing method.
Further, although the number of laminated electrodes and dielectric layers that can form one pair of counter electrodes will be described, it should be understood that any number may be used. The sheet method uses powders such as TiO ₂ and BaTiO ₃ made into a paste with an appropriate binder for a layer with a high dielectric constant, and steatite, phoristerite TiO ₂ , etc. for a layer with a low dielectric constant. This is a method in which the powder is made into a paste with a suitable binder, extruded using a die and rolled into a sheet, and the sheet thus obtained (dry green one) is used for lamination. The printing method is a method of laminating the above paste-like materials by printing. In the case of capacitor electrodes, the printing method is Pb,
This is a method in which heat-resistant metal powder such as Pd-Ag is made into a paste with an appropriate binder and then formed into a thin layer by printing. In the above, when referring to the sheet method and the printing method, they are used in the above meaning.

FIG. 1 shows a layer 1 having a high dielectric constant formed by a sheet method or a printing method. This layer 1 is actually formed as many sheets or one continuous sheet on a smooth wide-area substrate (not shown) such as an aluminum substrate, and many of the following steps are performed simultaneously in parallel. However, in order to simplify the explanation, only one circuit component will be explained. The size of the dielectric 1 is such that it can define the size of one solid-state integrated electronic circuit component. Moving on to the process shown in FIG. 2, at least one electrode 2 is formed on the surface of the dielectric 1 by a printing method. In the figure, four electrodes 2 are formed in parallel so as to form four capacitors C ₁ to C ₄ , and their upper ends are exposed at the upper edge of the dielectric 1 . Next, proceeding to the step shown in FIG. 3, a dielectric material 3 having a high dielectric constant similar to the dielectric material 1 is formed by a sheet method or by printing. Then the fourth
As shown in the figure, another electrode 4 is printed on the top surface of the dielectric 3. The electrodes 4 are four parallel electrodes that partially overlap the lower electrode 2, each having a capacitor function, and each having a lower end exposed at the lower edge of the laminate. Next, as shown in FIG. 5, a low dielectric material 5 consisting of an insulating layer having a lower dielectric constant than the internal dielectric layer 3 is further printed or superimposed (in the case of a sheet method) on the thus formed laminate. Use it as a shield. The purpose of this low dielectric layer 5 is to prevent the adverse effects of distributed capacitance formed between printed circuit patterns when a circuit formed thereon operates at a high frequency.

With the above steps, the lamination process before firing is completed. As mentioned at the beginning, since the above-mentioned laminate is actually formed in large numbers over a wide area at the same time, it is cut with an appropriate cutter after the process shown in FIG. 5 is completed. In this way, as shown in FIG.
The ends of the internal electrodes 2 and 4 are exposed on the two edge surfaces. Next, the cut laminate is placed in a firing furnace and fired at a predetermined temperature (eg, 1300 to 1400°C). Note that titanium oxide ceramic (dielectric layers 1 and 3) and steatite ceramic (layer 5)
In general, cracks may occur due to differences in thermal expansion coefficients, but it has been found that cracks can be prevented by selecting the particle size of these ceramics.

That is, if the average particle size and particle size distribution of the fired body of titanium oxide and steatite are appropriately selected,
The firing temperature dependence curves of both shrinkage rates can be made to almost match.

The obtained laminate forms capacitors C ₁ to _{C 4} in which a dielectric material is sandwiched between internal electrodes 2 and 4. Next, the laminate is held and fixed using a suitable jig (not shown), and the exposed ends of the internal electrodes 2 and 4 are drawn out to the surface of the laminate (the surface of the low dielectric material 5) as shown in FIG. That is,
A conductive metal powder paste of silver, silver palladium, etc. is applied to the surface of the laminate from the exposed ends of the electrodes 2, 4 and baked (for example, at 800° C.) or by other plating methods to form external terminals 7, 7'. In addition, a connecting terminal 8 is simultaneously formed on another edge (or the same edge may be used) for connection.

Thereafter, as shown in FIG. 8, a silver pattern 9 for a predetermined circuit configuration is formed by printing, baking, plating, or other methods commonly used in printed wiring. Next, as shown in FIG. 9, a resistor 10 (for example, ruthenium oxide powder paint) is applied and baked (for example,
). Finally, as shown in FIG. 10, elements such as the transistor 11 are soldered to complete the chip-shaped solid-state integrated circuit component of the present invention. In the embodiment, elements such as the resistor 10 and the transistor 11 are shown as electronic circuit components, but at least one arbitrary component may be provided as these electronic components. The completed part has the appearance shown in FIG.

As is clear from this example, in the circuit component of the present invention, the printed wiring board itself has at least one capacitor function due to the integrated internal electrodes and dielectric material, and at the same time, the circuit component of the present invention has at least one capacitor function. Since the lead-out portions of the electrodes are formed around the surface of the laminate, they can be easily connected to the printed wiring portion, and the other lead-out portions are also concentrated around the outer periphery of the laminate. Benefits include the ability to solder chip-like solid state integrated circuit components directly into larger printed circuit boards of electronic devices.

Application examples of the laminated circuit components shown in FIGS. 1-11 are shown in FIGS. 12-14. The circuit shown in FIG. 12 is an example of an intermediate frequency amplifier, and the first
~ C ₁ ~ _{C 4} in the circuit components obtained through the process shown in Figure 11
correspond to C ₁ to _{C 4} in this figure, R ₁ to _{R 8} are resistors baked on the surface of the stack, Q ₁ and Q ₂ are transistors soldered to the same surface, and T ₁
~ _T4 is a connection terminal exposed at the periphery of the laminate. The circuit shown in FIG. 12 has the arrangement shown in FIG. 13 or 14 on the surface of the laminate. That is, C ₁ to C ₄
The positive and negative external terminals of are exposed at the upper and lower edges of the laminate, and the printed wiring 9 connects the baked films of the resistors R ₁ to R ₈ (all 10 in FIGS. 10 and 11).
), transistors Q ₁ , Q ₂ (10th
11), a jumper 12 (means for preventing overlap between wiring lines), and connection terminals _T1 to _T4 .

It will be obvious to those skilled in the art that the above example is merely one example and that many other variations are possible. What is important is that the present invention has a dielectric and an electrode inside, and has various circuit elements and wiring on the surface. This greatly streamlines the integrated circuit manufacturing process and provides the benefits previously discussed.

[Brief explanation of the drawing]

Figures 1 to 11 show each stage of the manufacturing process of the solid-state laminated circuit component of the present invention. In Figures 1 to 5, the left side is a plan view, the right side is a sectional view through the electrode section, and Figure 6 is a perspective view. , FIG. 7 is a perspective view, FIG. 8 is a plan view, and FIG. 9 is a perspective view.
10 are partial plan views, and FIG. 11 is a partial perspective view. FIG. 12 is an application circuit of the completed solid-state laminated circuit component of the present invention. 13 and 14 are layout diagrams on the surface of the solid-state laminated circuit component of the present invention for realizing the circuit of FIG. 12. The main members in the figure are as follows. 1, 3: dielectric, 2, 4: capacitor electrode,
5: Low dielectric, 7, 7': External terminal, 8: Connection terminal.

Claims (1)

[Claims] 1. A layer of an insulator having a lower permittivity than the dielectric layer is provided on the surface of a laminate having multiple capacitor functions, which is formed by laminating and sintering an internal electrode layer and a dielectric layer, and a layer of an insulator having a dielectric constant lower than that of the dielectric layer is provided directly on the surface. Form a conductive layer for wiring,
The internal electrode layer is exposed on the edge surface of the laminate and electrically connected to the conductive layer formed on the surface of the laminate, and at least one electronic component is attached to the surface and electrically connected to the conductive layer. A solid-state laminated electronic circuit component characterized by: