JPS62219082A - Space filter circuit with code correction - Google Patents

Abstract

PURPOSE:To directly input picture data read out of a picture memory, to directly write its output in a picture memory and to attain a quick processing by providing the input and output sides of a multiplier and accumulator with hardware used for converting levels. CONSTITUTION:If an input A is codeless data of eight bits in a pre-processing circuit 2, a multiplexer 9 applies a signal from the side of a grounding pontential 10 as '0' to the side MSB of the input A, whereby it is converted into data of 12 bits with codes as a figure (a) shows. If the input A is data of eight bits with codes, the code bit of the input A is added to the side MSB of the input A as a figure (b) shows, and converted into data of 12 bits with codes.

Description

[Detailed Description of the Invention] [Summary] Multivalued (for example, 8-bit) image data that handles shading does not have the meaning of negative values. However, when image processing is performed using a spatial filter, a negative value is multiplied during the image processing, so that a negative value is generated in the processed image data. Furthermore, the input data to the spatial filter needs to be signed data. Therefore, conventionally, it has been necessary to perform 111I adjustment processing on these at the input/output section of the spatial filter, which has led to the problem that handling of precision and codes is complicated and processing speed is slow.

In view of these conventional problems, the present invention discloses the configuration of a spatial filter that does not require special processing during input/output and is capable of high-speed processing.

[Industrial application field]

The present invention relates to image processing, and particularly to the configuration of a spatial filter that performs a product-sum operation between pixel data to be processed and data on a table prepared in advance.

[Conventional technology]

When processing image data, the image data stored in the image memory is usually read out by raster scanning and processed, and the results are stored in the image memory. Image data is normally 8 bits when dealing with shading, and the bus for transferring the image is also 8 bits. Therefore, image data often takes an unsigned 8-bit data format. This relationship is shown in Figure 6. In the figure, 50 is the input image in the image memory (coded fi8 bit), and 51 is the processed image. , 5
2 indicates an output image (unsigned 8 bits) to be written into the image memory.

FIG. 7 is a diagram illustrating the processing of the spatial filter. In the same figure, 53 is table data (signed 8 bits)
, 54 indicates an input image (signed 8 bits), 55 indicates a 3×3 product-sum operation, and 56 indicates an output image (signed 19 bits). The table data 53 includes 3×3 negative values prepared in advance, and this is used to perform the sum-of-products operation on the pixel data in the input image 54, so the input image data is signed (8 bits). There must be.

The product-sum calculation 55 performs the calculation shown in the following formula.

Qxy= Σ P (x+t) (y+j)・T
tjt: -1 j = square, Qxy: value of the output pixel at the coordinates (x, y) Pxy: value of the input pixel at the base (x = y) Ttj: value of the 3X3 matrix coordinate (tyj).

As a result, the output image data is as shown in FIG.
This becomes signed 19-bit image data.

In this way, in the processing of this spatial filter, the input image data must be signed 8 bits, and
Since the output image data is signed 19 bits, when processing unsigned image data as described above, it is necessary to convert the level of the image data at the input and output sides of the spatial filter.

[Problem that the invention seeks to solve]

Figure plS8 shows the state of level conversion in the conventional spatial filter processing as described above. In the figure, 50.52.55 is! It is the same as the case of @6 figure or MS7 figure, 57.60 is level conversion, 58.59
shows the converted image.

The image data in the image memory input from the TV left camera is normally unsigned 8-bit information in the range of 0 to 255, so it is processed by the level conversion 57 to convert it to θ to +1.
27, or signed 8 in the range -128 to +128
Convert to bit data.

Then, a sum-of-products operation 55 is performed using signed values, and signed 19-bit data is output.

In this case, data is transferred using an 8-bit image bus, so
The 19-bit data is transferred several times. Finally, the level of the 19-bit data is converted into unsigned 8-bit data (for display on a display) and output as an output image 52.

As described above, the processing in the conventional spatial filter requires level conversion processing.

For example, if the product-sum calculation and the level conversion have the same processing speed, the processing time of the spatial filter will be three times the processing time of the product-sum calculation.

Therefore, there has been a problem in that the processing by the conventional spatial filter is slow.

In order to solve these conventional problems, the present invention aims to provide a spatial filter that does not require special processing such as level conversion on the input/output side and can perform high-speed processing. It is said that

[Means for solving problems]

According to the present invention, the above object is to provide a spatial filter for an image processing device that reads image data stored in an image memory by raster scanning and executes n x n local parallel operations using hardware. a circuit for converting signed or unsigned m-bit data read from an image memory into signed multi-bit data suitable for input to an n×n multiplication accumulator; This is achieved by a spatial filter circuit with sign correction characterized in that it includes a circuit that converts output signed multi-bit data into signed or unsigned m-bit data.

〔Example〕

FIG. 1 is a block diagram of one embodiment of the present invention, in which 1 is an 8-bit) x 9 table register, 2 is a preprocessing circuit, and 3 is a block diagram of an embodiment of the present invention.
is a 3×3 multiplication accumulator, 4 is a post-processing circuit, 51, 5□ is a line buffer, 6, to 6. is a multiplexer (M P
X), 71-7° is a 12-bit multiplication/accumulation circuit, 8. ．．
82 represents an adder. Reference symbols A to H represent signals or data, respectively. A is an input, F is one output, and each is signed or unsigned 8-bit data, B and D are signed 12-bit data, C. indicates signed 8-bit data, E indicates signed 20-bit data, and G is a selector for switching the mode depending on whether the input A of the preprocessing circuit 2 is signed or unsigned. The signal H represents a select signal for switching whether the output F of the post-processing circuit 4 is signed or unsigned.

FIG. 2 is a diagram showing an example of the configuration of the above-mentioned preprocessing circuit (2 in FIG. 1), where 9 is a 2:1 multiplexer (M
PX').

In FIG. 2, when the input A is unsigned 8-bit data, the multiplexer 9 outputs the ground potential 10
side is applied as 0″ to the MSB side of input A, and P
The data is converted into signed 12-bit data as shown in IS3 diagram (a). On the other hand, when input A is signed 8-bit data, the sign bit of input A is added to the MSB side of input A to create signed 12-bit data. is converted to In FIG. 3, the sign bit is designated by the reference symbol S.

tj & 4 is a diagram showing an example of the configuration of the post-processing circuit (4 in FIG. 1). ~11. represent a 13:1 multiplexer (MPX), respectively.

The tP55 diagram is a diagram showing the input/output relationship of the post-processing circuit.
(a) shows conversion to unsigned 8-bit data, and (b) shows conversion to signed 8-bit data. In the conversion to unsigned 8-bit data shown in (a), if the result of the product-sum operation is negative, it is forcibly set to zero. On the other hand, (b
), in the conversion to signed 8-bit data, the sign bit indicated by reference symbol S is shifted as is, and
Select 7 bits at arbitrary positions from bits other than the sign bit.

〔Effect of the invention〕

As explained above, since the spatial 7-ilter circuit with sign correction of the present invention is provided with hardware for level conversion on the input side and output side of the tree IL accumulator, the image data read from the image memory can be directly input, and the output can be written directly to the image memory6.And as these pre-processing and post-geography are done by hardware as mentioned above, very high-speed processing is possible. is possible.

Another advantage is that input and output can be easily switched between signed data and unsigned data using a select signal.

[Brief explanation of drawings]

Figure 1 is a block diagram of one embodiment of the present invention, Figure plS2 is a diagram showing an example of the configuration of the preprocessing circuit, Figure f@3 is a diagram explaining the input/output relationship of the preprocessing circuit, and Figure 4 is A diagram showing an example of the configuration of the post-processing circuit, PIS5 diagram is a diagram showing the input/output relationship of the post-processing circuit, fjS6 diagram is a diagram explaining image processing, FIG. 7 is a diagram explaining spatial filter processing, fJS8
The figure is a diagram explaining level conversion. 1...Table register, 2...
Pre-processing circuit, 3...3×3 power W, accumulator, 4...Post-processing circuit, 51.5□...
... Line buffer, 6, ~6ri...Multiplexer, 71~7. ...... 12-bit multiplication/accumulation circuit, 83,8□...Adder, 9
・・・・・・ 2:1 multiplexer, 10...
・Ground potential, 11... 13:17゛Multiplexer, -・, Agent Patent Attorney Igeta -m-゛°・Print 1 of the configuration of the preprocessing circuit Figure 2 Preprocessing @Route Figure 3 shows the control of the input and output of the circuit. Figure 3 shows an example of the efficiency of the post-processing circuit.・Figure 6 to explain the code V8 bit and the principle of the open filter Figure 7 Figure 7 to explain the principle of code fish θ bit level) L/conversion 1 to explain the figure 8

Claims (1)

[Claims] A spatial filter for an image processing device that reads out image data stored in an image memory by raster scanning and executes n×n local parallel operations using hardware. data n
A circuit that converts the signed multi-bit data that is suitable as the input of an xn multiplier accumulator, and the signed multi-bit data output from the multiplier accumulator to signed or unsigned m-bit data. 1. A spatial filter circuit with sign correction, characterized in that it includes a circuit for converting into.