JPS622335B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiprocessor system configured to perform restart processing in the event of a failure using a management processor.

In general, a multiprocessor system has one control program but multiple processors, and the processors, main storage, and input/output devices are connected through a single bus.
Each processor takes on a different function and processes data in parallel.

However, conventionally, in electronic exchange systems,
Due to the complexity of failure handling, a multiprocessor system in which a large number of processors are connected has not been realized.

The present invention has been made in view of the above circumstances, and allows complex failure processing to be performed by operating and processing other processors.
It is an object of the present invention to provide a multiprocessor system that can be applied to electronic exchange systems and the like, which is simplified by centrally managing it using a management processor that performs maintenance and management.

That is, the present invention is a multiprocessor system comprising a plurality of duplex processors and a data transfer device attached to each processor and transferring data between the processors via a bus. A management processor is provided to manage the operation and maintenance of other processors from among the plurality of processors mentioned above, and for each of the other processors,
When one of the duplexed processors goes down, it sends out a processor down signal and the other duplexed processor establishes a normal system, and displays the processor down signal as an external device of the management processor. The system is configured to perform restart processing in the event of a failure, including means for causing the management processor to read the data and means for causing the management processor to interrupt each of the processors.

Hereinafter, the present invention will be explained based on embodiments shown in the drawings.

FIG. 1 is a conceptual diagram showing an embodiment of the multiprocessor system of the present invention, and FIG. 2 shows details of the multiprocessor control device used in the above embodiment.
Also, it is a conceptual diagram showing the connection relationship between the control device and each processor. In the figure, the multiprocessor system of the present invention includes duplicated processors 10 to 12, a management processor 20, and a multiprocessor control device 30.

The processors 10 to 12 and the management processor 20 are each configured to be duplicated. The management processor 20 is set as a processor that operates and maintains other processors (processors 10 to 12 in this embodiment) from among a plurality of duplicated processors. On the other hand, the other processors 10 to 12 are processors that perform information processing, and are configured to send out a processor down signal when one of the duplexed processors goes down, and to establish a normal system using the other duplexed processor. Ru.

The above processors 10 to 12 and the management processor 2
0 is connected via a system bus 50a, and information is transferred via data transfer devices 101-121, 201 connected via signal lines 10a-12a and 20a, respectively. The bus control device 50 connected to the system bus 50a is connected to the system bus 50a.
a, and is controlled by the management processor 20 via the control signal line 20c. Further, input/output control devices 40 to 42 and a multiprocessor control device 30 are connected to the management processor 20 via an input/output bus 20b. Input/output control device 40~
42, the input/output bus 20b is the signal line 40a to 4.
2a, and is controlled by the management processor 20 to control input/output devices 401-421 via signal lines 40b-42b.

The multiprocessor control device 30 is composed of a control section 301, a processor down indication register 302 corresponding to each processor, and each processor interrupt control register 303.

This control unit 301 controls the management processor 20
, interprets the instructions input via the input/output bus 20b, and outputs the processor down indication register 302.
It discriminates whether to read the display for the processor interrupt control register 303 or to control the processor interrupt to each processor interrupt control register 303, and outputs a processor down display register read and reset signal 302a or a processor interrupt control signal 301a corresponding to each processor interrupt control register 303.

Processor down indication register 302 is set by a processor down signal sent via signal lines 10b to 12b when one of the duplicated processors goes down. Then, it is reset by a reset signal from the management processor 20.

The processor interrupt control register 303 receives the processor interrupt control signal 301a from the management processor.
It is possible to set/reset any one bit or all bits simultaneously. Processor interrupt control signals 303a-303c, which are output from processor interrupt control register 303, set or reset the corresponding one bit in interrupt cause registers 102-122 of each of duplexed processors 10-12. Interrupt cause register 102~
122 When the corresponding 1 bit is set, an interrupt occurs to the programs in the processors 10 to 12, and the programs in the processors 10 to 12 can determine that the interrupt is from the management processor 20.

Note that the number of bits in the processor down indication register 302 and the processor interrupt control register 303 is equal to the logical maximum logarithm of processors in the multiprocessor system. Although not shown in FIG. 2, there are a plurality of processor interrupt control registers 303, and therefore, there are a plurality of interrupt control signals for each processor 10 to 12. 10-12
Needless to say, there are multiple types of interrupts.

Next, the failure handling operation of the system according to the present invention will be explained.

The system failure restart procedure consists of the following five parts: First, the failure processor notifies the management processor of the failure, then the failure processor enters the stopped state after notification, and then,
The management processor notifies other processors that the partial system is down, and furthermore, the processors issue a processing completion report together with the partial system down notification.Finally, the management processor issues a restart command to all processors.

Below, the above five steps of operation will be explained in detail with reference to the drawings.

Fault notification from fault processor to managing processor.

When a fault that cannot be handled by software control occurs in each processor, its detection circuit (not shown in Figures 1 and 2) operates and sends a processor down signal to signal line 10b, 11b, or 12b. It is sent out in pulses through the At the same time, one of the duplicated normal systems is established.
Then, the bit corresponding to the faulty processor in the processor down indication register 302 of the multiprocessor control device 30 is set to 1. On the other hand, the management processor 20 periodically looks up the processor down indication register 302 via the input/output bus 20b under program control. By reading the processor down indication register 302, it is possible to know which processor pair has gone down due to a failure based on the bit position set to 1.

The faulty processor enters the stopped state after being notified of the fault.

This operation occurs after the faulty processor issues a processor down signal to the management processor 20.
A specific address of the microprogram of the processor is automatically set, one of the duplexed normal systems is established, and control is passed to the microprogram. In the microprogram, the data transfer device 101 shown in FIG.
Management processor 20 via 111 or 121
Thereafter, it is in a stopped state (software is in a stopped state, only the microprogram is running) while checking whether there is an interrupt from the management processor 20.

The management processor notifies other processors of partial system down.

Normally, in a load balancing system, each processor is related to each other and communicates information with each other via data transfer devices 101 to 121, as in this system, so if the communicating partner's processor goes down, , you need to know that fact.
Therefore, if any bit is set to 1 as a result of reading the processor down indication register 302, the management processor 20 sends an interrupt control signal to a processor other than the processor in question.
Generates an interrupt to other processors to notify them of partial system down. After the notification, the management processor 20 registers the processor down indication register 302.
Reset the corresponding bit.

The processor issues a completion report after processing in response to the partial system down notification.

The other processors that have been notified of the partial system down notification by an interrupt initialize information related to the faulty processor during online processing, and then notify the data transfer device 101, 111 or 111 that the processing has ended. 121 to the management processor 20.

The management processor issues a restart command to all processors.

After the management processor 20 issues a partial system down notification to each processor, each processor sends its processing completion report to the main storage of the management processor 20 (not shown in the figure). (included in the file) is monitored by Ruthin, and after receiving processing completion reports from all processors,
All bits in the processor interrupt control register 303 are set to 1 at the same time, and a restart command is sent to all processors at the same time. Each processor receives this command via an interrupt, learns that the faulty processor can operate normally, and starts transferring information via the data transfer devices 101 to 121 as before.

As explained above, the present invention allows the management processor to monitor the status of multiple processors, and if even one processor has an abnormality, it notifies the other processors with an interrupt, and after all processors have completed their processing, the management processor By configuring the system so that the restart command is issued to all processors at the same time, the entire system can be managed in one go, which has the effect of simplifying restart processing from complex multiprocessor failures.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram showing an embodiment of the multiprocessor system of the present invention, and FIG. 2 shows details of the multiprocessor control device used in the above embodiment.
Also, it is a conceptual diagram showing the connection relationship between the control device and each processor. 10-12...Processor, 20...Management processor, 30...Multiprocessor control device, 4
0-42...Input/output control device, 50...Bus control device, 101-121, 201...Data transfer device, 102-122...Interrupt cause register, 30
1...Control unit, 302...Processor down indication register, 303...Processor interrupt control register.

Claims (1)

[Scope of Claims] 1. A multiprocessor system comprising a plurality of duplex processors and a data transfer device attached to each processor and transferring data between the processors via a bus. , A management processor is provided to manage the operation and maintenance of other processors among the plurality of processors mentioned above, and when one of the duplexed processors goes down, it sends out a processor down signal and and a means for displaying the processor down signal to be read by the management processor, as an external device to the management processor, and a means for displaying the processor down signal to be read by the management processor; What is claimed is: 1. A multiprocessor system comprising means for causing an interrupt, and configured to perform restart processing in the event of a failure.