JPS62237814A - Error correction coding device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an error correction coding device.

[Prior Art] For example, when writing audio or images in the form of digital signals to a recording medium such as an optical disk, error correction is required to prevent defects in the recording medium, writing errors, and read failures due to dirt, dust, scratches, etc. It is well known to record a code by adding it to a recording signal.

Among these error correction codes, CIRC is used in DAD (digital audio disk) and is known as a system with high correction ability.

Nowadays, when performing CIRC encoding processing on a group of input digital audio signals, a processing method as shown in the functional block diagram of FIG. 2 has been standardized.

As shown in the figure, the human input signal is handled in units of 24 words and 1 block, with 8 bits as 1 word.

Continuously input digital audio signals are processed according to an algorithm as detailed below.

l) Continuously input digital audio signals are 2
It is considered to be parallel data of WinO to Win23 with 4 words as one block.

2) WinO~Win3. Win8 ~ Winl
1, Win16 to Win19 are delayed by two blocks by the delay element DI.

3) Within this delay element, data is scrambled (
Reorder)).

4) All data after scrambling is operated on the arithmetic circuit C2 to calculate the error correction code Ql-Q4. At this point, one block becomes a data group of 28 words including error correction codes Q1 to Q4.

5) A different delay is applied to each of the 28 words of data via the delay element D2, from 0 block every 4 blocks to 108 blocks.

6) The arithmetic circuit C3 calculates all the data after the delay processing to calculate error correction codes P1 to P4. At this point, one block of data includes error correction codes P1 to P4.
The block is a data group of 32 words.

7) Applying a delay of one block to every other word for all 32 words of data through the delay element D3,
q1-Q4. Each error correction code of PI NF2 is inverted, and WoutONWout23. QoutlxQo
ut4゜Poutl Send as 32 words of parallel data up to NPout4.

Although the above-mentioned processing is well known, various configurations can be considered as hardware for realizing this processing.

For example, a configuration in which the functional blocks shown in FIG. 2 are directly converted into hardware can be considered. However, with this method, the human signal is replaced with 28 words of parallel data and all data is processed in parallel.
There are problems in that the amount of wiring increases and processing becomes complicated.

On the other hand, the human input signal in Figure 2 is written into the memory, and the data is addressed from the memory, taking into account the amount of delay of each delay element D1-03, and the data is encoded in the memory with error correction coding. A method of sequential reading is known. With this configuration, a final formatted data string can be obtained by reading and writing data while appropriately addressing the memory, which simplifies processing and is effective in simplifying hardware.

The case where a digital audio signal is recorded on an optical disk has been explained above, but next, let us consider the case where a television still image signal is digitally recorded on an optical disk.
It differs from recording and reproducing digital audio signals in the following points.

1) The sampling frequency of the audio signal is 44.1
H2, whereas the video signal is 10-14MHz
It is.

2) An audio signal is a continuous signal, whereas a television still image signal is, for example, a unit signal of 1/30 seconds in the case of the NTSC system.

As can be seen from the above, continuous processing is the principle for audio signals (: IRC coding, etc.), and on the other hand, this is possible because the sampling frequency is low.

On the other hand, since the sampling frequency of video signals is high, it is difficult to make the responsiveness of optical discs follow this, and also because the processing speed of CIRC coding cannot keep up with the processing speed of frames. It is necessary to use a memory or the like to convert the time axis.

In this case, after the image is once stored in the frame memory, the image signal is sequentially read out in accordance with the transfer rate of the optical disk, and CIRC coding is performed on the image signal.

[Problems to be Solved by the Invention] However, when recording television still image signals on an optical disk, it is difficult to use a coding circuit that is based on the premise of continuously coding continuous signals in real time, in addition to frame memory. There are many system-wise redundant points, such as the need to have memory and the speed of the arithmetic circuit.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the problems of the prior art described above and to provide an error correction coding device capable of error correction coding of an image signal with a simple circuit configuration.

[Means for Solving the Problems] The error correction coding device of the present invention includes a conversion means for converting an analog image signal into a digital signal, and a periodic storage of the digital image signal obtained by the conversion means for each screen. The apparatus includes a storage means and a means for adding an error correction code to the data and performing error correction encoding by performing arithmetic processing while shifting or exchanging the data in the storage means.

[Examples] Hereinafter, the present invention will be described using examples with reference to the drawings.

FIG. 1 shows a block diagram of an error correction coding apparatus to which the present invention is applied as an embodiment of the present invention.

In FIG. 1, 2 is an analog/digital (^/D) converter that samples an input analog television signal at 4 fsc and converts it into an 8-bit digital signal, 4 is a digitized television signal, and a frame memory for storing the calculated error correction code; 6 a memory controller for accessing the frame memory 4; 8 a central processing unit (CPU); 10 a reference memory table for calculating the error correction code; 12 14 is a data bus, and 16 is an address bus. It shows.

The frame memory 4 shown in FIG. 1 has a configuration as shown in FIG. 3 schematically.

This memory 4 stores digital data as 8 bits per word, and has 32 rows (M(0,i) to
M (31, i)), 16384 columns (M (J, 0
) to M (j, 16383)). Note that i represents a column number and j represents a row number. 1 from the first line
The 2nd line to the 28th line is the first data area Ao+, the 13th line to the 16th line is the error correction code q, area 80 of ~q4, the 17th line to the 28th line is the second data area Ar,
2. Lines 29 to 32 contain error correction codes P, -P,
area Ap is configured.

The total memory capacity is therefore 16384 x 32 = 52
It is 4288 (bytes).

Next, the operation of the error correction coding apparatus shown in FIG. 1 will be explained with reference to FIG.

(Step Sl) First, when writing data, the address of the frame memory 4 is controlled as follows.

1 frame analog television image signal at 4 fs
When sampling with c, 477334 of 4 fsc
Requires counting. The one frame period is 1730 seconds when converted into time.

Among this sampling data, the frame memory 4 stores 81B samples per IH, 48111 samples per frame, a total of 816 x 481 = 392496 samples.

0 to 3924 according to the sample data to be memorized now.
A counter counting 95 is activated in the memory controller 6.

The 24 words of data input sequentially are called WO~W23 in one block, and the data is stored at addresses M(o,i)~ of the frame memory 4.
Record in M (23, i) in the order of input (i = 0 to 1635
3).

(Step S2) In this state, addresses M(o;j) to M(3,i),
M(8,i)~M(tt,i), M(16,I)1~
Only the data of M (19, i) is shifted to the left by two blocks to form M (0, i+2) to M (3, i+2).

M (8, i + 2) M ~ (11, i + 2) , M (16
, i+2) to M(19, i+2).

(Steps S3, 54) In this case, the data protruding from the left end is enlarged sequentially from the right end of the same row.

Note that in this case, the row number N to which data should be shifted is given by: However, TNT is an integer conversion (rounding down to the nearest whole number).

[Step SS] Next, scrambling is performed between each line.
7,1) Wl4, WIS-M (24,i),
M (25, 1) W6. W, -M(22,i)
, M(23,1)W2. W3 → M(8, i),
M(7,+)W8. W9 → M(2,i), M(
3,1) Wl. , W++ −M(8,i) ,M(
9,1) Wllll, Wl9 → M(10,i),
M(11,i)” l 2 + W + 3 →
This is carried out through the following processing: M (18, i), M (19, 1) W5'' W 7 W6 ° Wl6. Note that → represents 6 movements on the frame memory, and → represents exchange.

In this process, the own destination row address 80 can be calculated as follows.

If j-0 to 23, However, in INT, only the integer part of the operation result is valid.

(Step S6) After the above processing, the correction code Q1. Calculate Q2, Q3, and Q4. In this case, a well-known matrix operation is performed in the CPU while referring to the reference memory table 10.

The calculation result is Q+ → M(12,1) Q2 → M(13,1) Q3 - M (14,1) Q4 = M (15, i) Store in.

(Step S7) After that, addresses M (0, i) to M (27, i) are shifted to the left, and for each row number j, the number of blocks to be shifted is jX4.

[Step S8. S9) In this case, the data that protrudes from the left end is inserted by shifting it sequentially from the right end of the same row.

(Step 510) Next, using the data M (0, i) to M (27, i), a correction code PlJ P2. P3. Calculate P4. In this case, the calculation is performed in the CPU while referring to the reference memory table IO, but this calculation can also be performed by matrix calculation or division.

The calculation result is Pl → M (28, 1) P2-M (29, i) P, -M(30,f) P4 → M (31, i) Store in.

(Step Sll) After that, only the data in even-numbered rows is shifted to the left by one block.

[Step 512] Next, data M(2,
8,i) to M(31,i) are all inverted.

[Step S12] After that, the data is transferred from the frame memory 4 to M (0, 0
)~M(31,0), M(0,1)~M(31,
1)...M(0°18353) to M(31,1835
3) is read out in the order of EFM (8
→14 conversion modulation), and sends a 3-bit DSV code to a recording system (not shown).

According to the configuration as described above, 1) The memory for storing image data can be shared as a memory for conversion when cross-interleaved Reed-Solomon encoding is performed, so that memory can be saved.

2) Since the image data memory acts as a buffer for time adjustment, the arithmetic circuit does not need high speed. Therefore, whereas conventionally table references were frequently used to increase speed, Algorithms allow address and data calculations, which saves memory.

3) By periodically multiplying each screen worth of image data by l by CIRC, it is possible to reduce the memory for storing image data for error correction encoding processing and record the image data on an optical disk or the like.

In addition, in the above embodiment, the case where CIRC acts periodically on one unit of data group was exemplified, but by providing a redundant area for the influence of CIRC in the frame memory, it is possible to It is also possible to have a configuration in which the effects are applied sequentially, as shown in the figure, and in this case, it becomes possible to record moving image data.

Further, in the above embodiments, the CIRC code is used as an example, but it goes without saying that the present invention is not limited to this and can be applied to various cross-interleave codes.

[Effects of the Invention] As described above, according to the present invention, it is possible to obtain an error correction coding device capable of error correction coding of an image signal with a simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an error correction coding device to which the present invention is applied as an embodiment of the present invention, and FIG. 2 is a block diagram of a CIRC
FIG. 3 is a schematic diagram of the frame memory of FIG. 2, and FIG. 4 is a flowchart of the main operations of the present invention. 2.-A/D converter, 4.. Frame memory, 6.. Memory controller, 8.. CPt1. 10... Reference memory table, 12... Modulation circuit.

Claims (1)

[Scope of Claims] Conversion means for converting an analog image signal into a digital signal; storage means for periodically storing the digital image signal obtained by the conversion means for each screen; and data in the storage means. An error correction coding device characterized by comprising means for adding an error correction code to the data and performing error correction encoding by performing arithmetic processing while shifting or exchanging the data.