JPS62244156A - 表面実装用パツケ−ジ - Google Patents

表面実装用パツケ−ジ

Info

Publication number
JPS62244156A
JPS62244156A JP61087834A JP8783486A JPS62244156A JP S62244156 A JPS62244156 A JP S62244156A JP 61087834 A JP61087834 A JP 61087834A JP 8783486 A JP8783486 A JP 8783486A JP S62244156 A JPS62244156 A JP S62244156A
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
package
pin
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61087834A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0519985B2 (2
Inventor
Osamu Fujikawa
治 藤川
Hiroshi Katsukawa
勝川　博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP61087834A priority Critical patent/JPS62244156A/ja
Publication of JPS62244156A publication Critical patent/JPS62244156A/ja
Publication of JPH0519985B2 publication Critical patent/JPH0519985B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
JP61087834A 1986-04-16 1986-04-16 表面実装用パツケ−ジ Granted JPS62244156A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61087834A JPS62244156A (ja) 1986-04-16 1986-04-16 表面実装用パツケ−ジ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61087834A JPS62244156A (ja) 1986-04-16 1986-04-16 表面実装用パツケ−ジ

Publications (2)

Publication Number Publication Date
JPS62244156A true JPS62244156A (ja) 1987-10-24
JPH0519985B2 JPH0519985B2 (2) 1993-03-18

Family

ID=13925960

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61087834A Granted JPS62244156A (ja) 1986-04-16 1986-04-16 表面実装用パツケ−ジ

Country Status (1)

Country Link
JP (1) JPS62244156A (2)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998034443A1 (en) * 1997-01-30 1998-08-06 Ibiden Co., Ltd. Printed wiring board and manufacturing method therefor
US6518513B1 (en) 1997-06-06 2003-02-11 Ibiden Co. Ltd. Single-sided circuit board and method for manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4875566U (2) * 1971-12-20 1973-09-19
JPS607752A (ja) * 1983-06-27 1985-01-16 Fujitsu Ltd 半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4875566U (2) * 1971-12-20 1973-09-19
JPS607752A (ja) * 1983-06-27 1985-01-16 Fujitsu Ltd 半導体装置の製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998034443A1 (en) * 1997-01-30 1998-08-06 Ibiden Co., Ltd. Printed wiring board and manufacturing method therefor
US6444924B1 (en) * 1997-01-30 2002-09-03 Naoto Ishida Printed wiring board with joining pin and manufacturing method therefor
US6518513B1 (en) 1997-06-06 2003-02-11 Ibiden Co. Ltd. Single-sided circuit board and method for manufacturing the same
US7721427B2 (en) 1997-06-06 2010-05-25 Ibiden Co., Ltd. Method for manufacturing single sided substrate

Also Published As

Publication number Publication date
JPH0519985B2 (2) 1993-03-18

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