JPS6224733A - Switching control system - Google Patents

Abstract

PURPOSE:To prevent mis-matching for the changeover to the coding system optimized to a MODEM at coder and decoder sides even if noise exists in a transmission line by detecting a phase change to detect a training signal in the adaptive differential coding system and using the detection signal for changeover. CONSTITUTION:When the training signal of patterns A, B is inputted to a signal detection circuit 18, a positive value is consecutive in the output of a zero cross identifier 19 as shown in figure (a). A counter 20 increments the count by '1' or clears the count depending whether the output of the identifier 19 is positive or negative. A comparator 22, when the count exceeds a value '100' shown in the figure, retards the locking of the circuit 18 via a F/F 25 to detect surely the end of the patterns. When the count exceeds a value '300' shown in the figure, a comparator 21 brings the output of a F/F 24 to level 1. Thus, when the pattern is finished and the output of the identifier 19 is a negative, an AND circuit 27 outputs '1' level and an output of a F/F 26 allows a coder to switch a quantizer and a forecast device semi-fixedly and fixedly and allows a decoder to switch an inverse quantizer and a forecast device.

Description

[Detailed Description of the Invention] [Summary] Signal detection circuits are used to detect training signals on both the encoder and decoder sides, and by using the output of the signal detection circuits to switch to an encoding method optimized for the modem, the decoder This is to prevent mismatching between switching on the encoder side and switching on the encoder side due to noise in the transmission path.

[Industrial application field]

The present invention relates to an improvement in a switching control method for an adaptive differential encoding method that switches an encoding method optimized for a voice signal to an encoding method optimized for a modem by detecting a modem training signal.

The above-mentioned adaptive differential encoding method applies the adaptive differential encoding method for voice signals, for which the present applicant applied for a patent in 1985, to the existing communication network. The following, of course, also enables data transmission of 9600 bps or more, and has the configuration described below.

FIG. 4 is a block diagram of an encoder using the adaptive differential encoding method, and FIG. 5 is a block diagram of a decoder using the adaptive differential encoding method.

In the figure, 1.3.7 is an adder, 2 is a semi-fixed/adaptive quantizer,
4.8 is a fixed/adaptive predictor, 6 is a semi-fixed/adaptive inverse quantizer, and 5 and 9 are training signal detectors.

The adaptive differential encoding encoder shown in FIG. 4 operates as an adaptive differential encoder with quantizer 2 as an adaptive quantizer and predictor 4 as an adaptive predictor when the input signal is an audio signal. When using a modem, when the first training signal to be sent is detected by the training signal detector 5, the quantizer 2 and the predictor 4 are changed to a semi-fixed quantizer, which is optimal for the modem.
It switches to the stator measuring instrument and sends out the differentially encoded signal to the transmission line.

The decoder using the adaptive differential encoding method shown in FIG. When the predictor 8 is an adaptive descape generator and an adaptive predictor, respectively, and the training signal detector 9 detects the training signal,
Semi-fixed inverse quantizer.

This is to switch to a stator measuring instrument.

When this latter encoder switches to a semi-fixed inverse quantizer and a stator measuring instrument by detecting a training signal, it is desirable to avoid mismatching with the switching on the encoder side due to noise in the transmission path.

[Conventional technology]

FIG. 6 is a block diagram of a conventional training signal detector.

In the figure, 10 is a 500Hz band pass filter, 11 is 1
A 700 Hz band pass filter, 12 a 2900 Hz band pass filter, 13 to 15 comparators, 16 an AND circuit, and 17 a counter.

Training sent from the modem (No. 8 is 500H)
A and B are simple repeating waveforms composed of composite sine waves with frequencies of 1700Hz, 2900Hz.
It's a pattern.

This training signal is passed through ζ5 Q OHz bandpass filter 10.1700Hz bandpass filter 11.2
The outputs of the comparators 13 to 15 pass through a 900 Hz band pass filter 12 and are compared with threshold values, and the outputs of the comparators 13 to 15 that are at a higher level are ANDed by an AND circuit 14. After the output becomes level, the counter 17 counts until the input signal level becomes constant, and then both the encoder and decoder are switched to the side most suitable for the modem.

[Problem that the invention seeks to solve]

However, if there is noise in the transmission path, the input signal may have a level change as shown in FIG. 7, although it would have the characteristics shown in A in the absence of noise, as shown in FIG.

Therefore, on the decoder side, when the comparators 13 to 15 in FIG. point, resulting in a temporal difference of Δ.

For this reason, a time difference of Δ may occur when switching between the encoder side and the decoder side, and there is a problem of mismatching during this time.

[Means for solving problems]

The problem mentioned above is that both the encoder and decoder sides use phase synchronization circuits for detecting training signals, which have a function of varying the amount of feedback and can perform pull-in operation within a limited frequency range, to synchronize the input signal. This problem is solved by the switching control method of the present invention, which uses a signal detection circuit that detects a signal based on the sign of the DC signal after performing synchronous detection with the signal, and uses this output to switch to an encoding method optimized for the modem. .

[Effect]

In the present invention, the signal detection circuit that detects a signal based on the sign of the DC component as a result of phase synchronization and synchronous detection detects the signal phase-wise and not based on power. Focusing on the point that there is no effect due to addition, the repetitive waveform of the input training signal (for example ■
, 29 modem training signal patterns A and B) to detect the training signal, reduce the amount of feedback of the phase synchronization circuit to slow down the tracking time, and set the end of the training signal to the phase synchronization circuit. Capture the moment when the withdrawal state is removed, and use this as a standard.
Since switching is made to the side optimized for the modem, there will be no mismatching when switching between the encoder side and the decoder side.

〔Example〕

FIG. 1 is a block diagram of a training signal detector according to an embodiment of the present invention, FIG. 2 is a time chart of switching point detection in the case of FIG. 1, and FIG. 3 is a signal detection circuit 1 of FIG.
FIG. 8 is a block diagram showing details of FIG.

In the figure, 18 is a signal detection circuit, 19 is a zero crossing discriminator, 20 is a counter, 21.22 is a comparator, 23 is a not circuit, 2
4 to 26 are flip-flops, 27 is an AND circuit, 28
．． 30 is a filter, 29. 31 to 34 are multipliers, 35.
36 is a delay element, 37 is a limiter, 38 is an adder, 39
is a code detector, and 40 is a phase locked loop (PLL circuit).

The signal detection circuit shown in FIG. 3 uses a phase synchronization circuit 40 that can perform pull-in operation within a limited range around the frequency of the sine wave signal, and performs synchronous detection of the sine wave signal using a multiplier 2.
By detecting that there is no change in sign of the DC component resulting from passing through This is a signal detection circuit for which the present applicant applied for a patent in 1985, eliminating the influence of noise.

That is, the sine wave signal Cosθ°n passed through the filter 28
and the imaginary component 5in(θ.+ω
) n in the multiplier 31, a sign detector 39 detects whether the signal is positive or negative, a multiplier 34 multiplies its output by a positive constant α of a small value, and the output is added. Vessel 3
8. Limiter 37. A signal e″0 is obtained from the output frequency ω of the integrating circuit that limits the offset frequency consisting of the delay element 36 and the input 1, and the multiplier 3 of the phase synchronization circuit 40 obtains a signal e″0.
2, the frequency that the oscillator that inputs the signal ejkl can pull in is limited to the range of ω, and θ°・θ. +ω, and the multiplier 29 converts the real component Co S(θ.+
ω)n and the output Cosθ°n of the filter 28 to the multiplier 2
9 to obtain a DC component and a frequency component double the input frequency, the filter 30 extracts the DC component, and the zero crossing discriminator 19 monitors the signal for a predetermined period of time. Detecting frequency components.

Here, θ°=2πfc'/fs However, fc" = Gear 9 frequency fs = Sampling frequency When used in the case of FIG.
The signal sampled at z will be input.

Next, training signal detection will be explained using FIGS. 1 and 2.

When the 1700 Hz training signals of patterns A and B are input to the signal detection circuit 18, as explained above,
The output of the zero crossing discriminator 19 continues to have positive values as shown in FIG.

The counter 20 counts the number of m consecutive times in which the sign is positive, and increases the count by 1 when the output of the zero crossing discriminator 19 is positive, and increases the count by 1 when the output is negative. Clear to 0.

The comparator 22 compares the count number with a value of 100, which is the time at which the training signal is expected to reach a certain level. /4 to reduce the amount of feedback for correcting the offset frequency component, slow down the pull-in operation, and make it possible to reliably detect the end of the A and B patterns.

The comparator 21 compares it with a value of 300, which is slightly less than the expected mu time of the A and B patterns, and if it exceeds this value, the output of the flip-flop 24 is set to 1 level and is input to the AND circuit 27.

If this is done, <A> as shown in FIG.

When the B pattern ends and the output of the zero-crossing discriminator 17 becomes a negative value, Lebel is outputted from the output of the AND circuit 27 via the NOT circuit 23, inputted to the flip-flop 26, and the output from the output of the flip-flop 26 is output. , in the encoder of FIG. 4, the quantizer 2. The predictor 4 is switched between semi-fixed and fixed, respectively, and in the decoder of FIG. 5, the inverse quantizer 6. Predictor 8 is semi-fixed.

Switch to fixed.

In other words, if the signal is detected by phase changes in this way, it will not be affected by noise in the transmission path, so there will be no mismatching between the encoder and decoder when switching to the modem-optimized encoding method. You won't have to do anything.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the training signal is detected by phase change, so it is not affected even if there is noise in the transmission path, so it is optimized for the modem on the encoder and decoder sides. This has the effect of eliminating mismatching when switching between different encoding methods.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a training signal detector according to an embodiment of the present invention, FIG. 2 is a time chart of switching point detection in the case of FIG. 1, and FIG. 3 shows details of the signal detection circuit 18 of FIG. 1. Figure 4 is a block diagram of an encoder using adaptive differential encoding; Figure 5 is a block diagram of a decoder using adaptive differential encoding; Figure 6 is a block diagram of a conventional training signal detector. , FIG. 7 is a characteristic diagram showing the level change of the training signal due to noise. In the figure, 2 is a semi-fixed/adaptive quantizer, 4.8 is a fixed/adaptive predictor, 5.9 is a training signal detector, 6 is a semi-fixed/adaptive inverse quantizer, 10 is a 500Hz bandpass filter, 11 is 1700
H,z band pass filter, 12 is a 2900 Hz band pass filter, 13 to 15, 22.23 are comparators, 16.27 is an AND circuit, 17.20 is a counter, 18 is a signal detection circuit, 19 is a zero crossing discriminator , 23 is a knot circuit, 24 to 26 are flip-flops, 28.30 is a filter, 29.31 to 34 are multipliers, 35.36 is a delay element, 37 is a limiter, 39 is a sign detector, 40 is a phase locked circuit shows. Agent J ``Buido Igata Sada - Winter 1 Ash 1's Breaking Base R's Kirichi 9 Kaneshi ω9. Imtate Year 2 Figure Decoder's Bron 2 Prisoner Haya 5 Figure

Claims (1)

[Claims] In an adaptive differential encoding method in which an encoding method optimized for a voice signal is switched to an encoding method optimized for a modem by detecting a training signal of a modem, training for both the encoder and decoder sides is provided. For signal detection, phase synchronization is achieved using a phase synchronization circuit that has a function of varying the amount of feedback and can perform pull-in operation within a limited frequency range, and the sign of the DC signal is determined after synchronous detection with the input signal. A switching control method characterized in that a signal detection circuit that detects a signal is used, and the output thereof is used to switch to an encoding method optimized for the modem.