JPS6225518B2 - - Google Patents
Info
- Publication number
- JPS6225518B2 JPS6225518B2 JP56160906A JP16090681A JPS6225518B2 JP S6225518 B2 JPS6225518 B2 JP S6225518B2 JP 56160906 A JP56160906 A JP 56160906A JP 16090681 A JP16090681 A JP 16090681A JP S6225518 B2 JPS6225518 B2 JP S6225518B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- signal
- thermal head
- tape carrier
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 239000010409 thin film Substances 0.000 claims description 2
- 239000010408 film Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Electronic Switches (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Description
【発明の詳細な説明】
本発明は、小型にして動作速度が速く、かつ高
密度実装が可能なサーマルヘツドの製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a thermal head that is small in size, has high operating speed, and can be mounted at high density.
従来、発熱抵抗素子1と、ダイオード2等の半
導体素子を搭載したサーマルヘツドは、第1図の
ように回路の二層配線実装を実現するために、共
通配線すべき信号線(1〜m)を二層配線素子
3、または厚膜素子等による二層配線を行なつて
いた。 Conventionally, a thermal head equipped with a heat generating resistor element 1 and a semiconductor element such as a diode 2 is equipped with a signal line (1 to m) that should be commonly wired in order to realize a two-layer wiring implementation of the circuit as shown in Fig. 1. Two-layer wiring was performed using a two-layer wiring element 3 or a thick film element.
第1図における実線は素子の配線およびリー
ド、破線はサーマルヘツド基板の配線を示す。4
は外部に取り出すための信号線である。 In FIG. 1, solid lines indicate the wiring and leads of the element, and broken lines indicate the wiring of the thermal head board. 4
is a signal line for taking out to the outside.
しかしながら、この実装方法によると、二層配
線素子3、または厚膜素子を使用するため、実装
スペースを広くとる必要があること、配線工数が
かかつてコスト高となる欠点があつた。 However, according to this mounting method, since the two-layer wiring element 3 or the thick film element is used, a large mounting space is required, and the number of wiring steps is long, resulting in high cost.
また、第2図のようにテープキヤリア6を使用
した二層配線技術もあるが、いずれも前述したよ
うな欠点があつた。ただし、テープキヤリア6を
使用した場合、そのテープ上にダイオード2等の
半導体素子をインナーリードボンデイングした
後、基板へのアウターリードボンデイングが自動
でできるため工数は減少するが、第2図のように
実装スペースを大きくとるという欠点は解決され
ていなかつた。 There is also a two-layer wiring technique using a tape carrier 6 as shown in FIG. 2, but both have the drawbacks mentioned above. However, when using the tape carrier 6, after inner lead bonding of semiconductor elements such as the diode 2 on the tape, outer lead bonding to the board can be automatically performed, reducing the number of man-hours, but as shown in Figure 2. The disadvantage of requiring a large amount of mounting space remained unsolved.
なお、第2図における実線はテープキヤリアを
含めた素子の配線およびリード、破線はサーマル
ヘツド基板の配線を示す。 In FIG. 2, the solid lines indicate the wiring and leads of the elements including the tape carrier, and the broken lines indicate the wiring of the thermal head board.
本発明は、これらの欠点を除去するため、IC
等の半導体素子の共通配線をするべき信号線の電
極である信号パツトと、該信号パツトの端子数と
同数のダミーパツトとを左右対称に前記半導体素
子内に配置形成する。そして、これらをテープキ
ヤリアにインナーリードボンデイングし、前記
個々の信号パツトとダミーパツトとをそれぞれ接
続した後、前記テープキヤリアをアウターリード
ボンデイングするように構成したものである。 The present invention eliminates these drawbacks by
Signal pads, which are electrodes of signal lines to be used as common wiring for semiconductor devices such as the above, and dummy pads, the same number as the number of terminals of the signal pads, are arranged and formed symmetrically within the semiconductor device. These are then inner lead bonded to the tape carrier, and after the individual signal pads and dummy pads are connected, the tape carrier is outer lead bonded.
これにより、ボンデイング工数の減少と、実装
スペースを小さくする二層配線を実現したもので
ある。 This reduces bonding man-hours and realizes two-layer wiring, which reduces mounting space.
以下、本発明の実施例を図にしたがつて詳細に
説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
まず、第3図のように、サーマルヘツド基板上
に搭載するIC10等の半導体素子の共通配線を
するべき信号線の電極である信号パツト11と、
該信号パツト11の端子数と同数の電極のみで他
の配線がないダミーパツト12とを前記IC10
内に左右対称となるように半導体表面に膜形成
し、ホトリソエツチングおよびメツキにより配置
形成する。次に、これらを第4図に示すようにテ
ープキヤリア6にインナーリードボンデイング
し、個々の信号パツト11の1〜mとダミーパツ
ト12の1′〜m′とをそれぞれ接続する。第4図の
13はテープ上の配線を15は基板上の薄膜パタ
ーンを示す。しかる後に、第5図Aのようにサー
マルヘツド基板上にICチツプ等がインナーリー
ドボンデイングされたテープキヤリア6を基板上
の導膜パターン15とアウターリードボンデイン
グする。第5図Bは側面からみた状態を示したも
のである。第5図Aにおける破線はサーマルヘツ
ド基板の配線、細線および太線はテープキヤリア
の配線およびリードを示す。 First, as shown in FIG. 3, a signal pad 11, which is an electrode of a signal line to be used as a common wiring for semiconductor elements such as an IC 10 mounted on a thermal head substrate,
A dummy pad 12 having the same number of electrodes as the number of terminals of the signal pad 11 and no other wiring is connected to the IC 10.
A film is formed on the surface of the semiconductor so that it is left and right symmetrical, and the film is arranged and formed by photolithography and plating. Next, as shown in FIG. 4, these are inner lead bonded to the tape carrier 6, and the individual signal pads 11 1-m and the dummy pads 12 1'-m' are connected, respectively. In FIG. 4, reference numeral 13 indicates wiring on the tape, and reference numeral 15 indicates a thin film pattern on the substrate. Thereafter, as shown in FIG. 5A, the tape carrier 6 on which IC chips and the like are inner lead bonded on the thermal head substrate is outer lead bonded to the conductive film pattern 15 on the substrate. FIG. 5B shows the state seen from the side. In FIG. 5A, broken lines indicate the wiring of the thermal head board, and thin and thick lines indicate the wiring and leads of the tape carrier.
また、IC101から1、IC201から2、IC
301からmの信号線4を外部に取り出してい
る。この信号線は、いずれのICから取り出すこ
ともでき、信号線の順序(配列)も適宜選択でき
る。 Also, IC101 to 1, IC201 to 2, IC
Signal lines 4 from 301 to m are taken out to the outside. These signal lines can be taken out from any IC, and the order (arrangement) of the signal lines can be selected as appropriate.
この様な構成手段により隣接したIC10の信
号線を簡単に接続することができ、しかも少ない
スペースで二層配線が可能となる。 With such a configuration means, signal lines of adjacent ICs 10 can be easily connected, and furthermore, two-layer wiring is possible with a small space.
このようなサーマルヘツドを動作するには、例
えばIC101の1パツトの信号はテープキヤリ
ア6を通つてアウターリードボンデイング部14
から基板上の配線を通過し、IC201の1パツ
トに入いる。以下IC301も同様とし、信号パ
ツト11の2〜mの信号も同様になる。 To operate such a thermal head, for example, a signal from one part of the IC 101 is passed through the tape carrier 6 to the outer lead bonding section 14.
From there, it passes through the wiring on the board and enters one part of IC201. The same applies to the IC 301 below, and the signals 2 to m of the signal pad 11 also apply in the same manner.
なお、信号の種類によつて隣接チツプに接続す
る必要のない場合は、基板の配線をカツトすれば
良い。 Note that if there is no need to connect to an adjacent chip depending on the type of signal, the wiring on the board may be cut.
以上説明したように本発明によれば、工数的に
少なく、実装スペース的にも小さく二層配線が実
現できるので、高密度実装が可能となり、かつ低
コストで小型化されたサーマルヘツドを得ること
が出来る利点がある。言い換えれば、
1 テープキヤリアを使用することによつて自動
ボンデイングが可能なこと。 As explained above, according to the present invention, two-layer wiring can be realized with fewer man-hours and a smaller mounting space, making it possible to achieve high-density mounting and to obtain a thermal head that is miniaturized at low cost. It has the advantage of being able to In other words: 1. Automatic bonding is possible by using a tape carrier.
2 多層配線のスペースが不要(大部分のスペー
スはICチツプの下側の基板で可能)なため、
高密度実装された小型のサーマルヘツドが実現
できる。(従来のヘツドに対し約1/2の大きさに
できる。)2. No space is required for multilayer wiring (most of the space can be taken up on the board below the IC chip);
A compact thermal head with high density packaging can be realized. (It can be made approximately 1/2 the size of a conventional head.)
第1図および第2図は従来のサーマルヘツドの
二層配線部の説明図、第3図は本発明の実施例を
説明するためのICチツプ図、第4図は本発明の
実施例を説明するためのICチツプとテープキヤ
リアのボンデイング図、第5図Aは本発明の実施
例を説明するための実装図、第5図Bはその側面
図。である。
6……テープキヤリア、10……IC等の半導
体素子、11……信号パツト、12……ダミーパ
ツト、13……テープ上の配線、14……ボンデ
イング部。
Figures 1 and 2 are explanatory diagrams of the two-layer wiring section of a conventional thermal head, Figure 3 is an IC chip diagram for explaining an embodiment of the present invention, and Figure 4 is an illustration of an embodiment of the present invention. FIG. 5A is a mounting diagram for explaining an embodiment of the present invention, and FIG. 5B is a side view thereof. It is. 6... Tape carrier, 10... Semiconductor element such as IC, 11... Signal pad, 12... Dummy pad, 13... Wiring on tape, 14... Bonding part.
Claims (1)
するサーマルヘツドにおいて、IC等の各半導体
素子の共通配線をするべき信号線の電極である信
号パツトと、該信号パツトの端子数と同数のダミ
ーパツトとを左右対称に前記半導体素子内に配置
形成し、これらをテープキヤリアにインナーリー
ドボンデイングすることによつて、前記個々の信
号パツトとダミーパツトとをそれぞれ接続した
後、前記テープキヤリアを基板上の薄膜パターン
とアウターリードボンデイングすることを特徴と
するサーマルヘツドの二層配線部の製造方法。1. In a thermal head that mounts a heat generating resistor element and a semiconductor element such as an IC, a signal pad which is the electrode of the signal line to be used as a common wiring for each semiconductor element such as an IC, and dummy pads of the same number as the number of terminals of the signal pad. are arranged symmetrically within the semiconductor element, and are connected to the individual signal pads and dummy pads by inner lead bonding to the tape carrier, and then the tape carrier is bonded to a thin film on the substrate. A method for manufacturing a two-layer wiring part of a thermal head, characterized by bonding a pattern and an outer lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56160906A JPS5862076A (en) | 1981-10-12 | 1981-10-12 | Manufacture of double layered wiring part of thermal head |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56160906A JPS5862076A (en) | 1981-10-12 | 1981-10-12 | Manufacture of double layered wiring part of thermal head |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5862076A JPS5862076A (en) | 1983-04-13 |
| JPS6225518B2 true JPS6225518B2 (en) | 1987-06-03 |
Family
ID=15724888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56160906A Granted JPS5862076A (en) | 1981-10-12 | 1981-10-12 | Manufacture of double layered wiring part of thermal head |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5862076A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6034023A (en) * | 1983-08-04 | 1985-02-21 | Oki Electric Ind Co Ltd | Mounting of semiconductor chip on substrate |
| JPS60143641A (en) * | 1983-12-29 | 1985-07-29 | Konishiroku Photo Ind Co Ltd | Integrated circuit device |
-
1981
- 1981-10-12 JP JP56160906A patent/JPS5862076A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5862076A (en) | 1983-04-13 |
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