JPH04159765A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPH04159765A
JPH04159765A JP2284898A JP28489890A JPH04159765A JP H04159765 A JPH04159765 A JP H04159765A JP 2284898 A JP2284898 A JP 2284898A JP 28489890 A JP28489890 A JP 28489890A JP H04159765 A JPH04159765 A JP H04159765A
Authority
JP
Japan
Prior art keywords
lead frame
integrated circuit
printed wiring
circuit device
semiconductor bare
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2284898A
Other languages
Japanese (ja)
Other versions
JP2595803B2 (en
Inventor
Hideto Nitta
新田　秀人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2284898A priority Critical patent/JP2595803B2/en
Publication of JPH04159765A publication Critical patent/JPH04159765A/en
Application granted granted Critical
Publication of JP2595803B2 publication Critical patent/JP2595803B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To facilitate high integration, high density by bringing a second lead frame in which a printed circuit board placed with at least two semiconductor bare chips is adhered to one side surface into contact with a first lead frame face, superposing them and resin-sealing it. CONSTITUTION:A printed circuit board 2b is adhered on a lead frame 1b, two semiconductor bare chips 3b are placed on the board 2b by die bonding, further the chip 3b is connected to the board 2b and the board 2b is connected to the frame 1b by wire bonding with gold wires 5b. Then, the frames 1a, 1b are superposed on the surfaces in which the boards 2a, 2b are not adhered, and sealed with resin 5 by a transfer molding method. Thus, high density and high integration are facilitated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路装置に関し、特に半導体ベアチッ
プを樹脂封止した混成集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit device, and more particularly to a hybrid integrated circuit device in which a semiconductor bare chip is sealed with resin.

〔従来の技術〕[Conventional technology]

従来、リードフレーム上に絶縁エリアを設け、その上に
所定の配線が施されたプリント配線基板を貼り付け、プ
リント配線基板上の所定の位置に半導体素子等をベアチ
ップ状態にて搭載し、ベアチップとプリント配線基板間
およびプリント配線基板とリードフレーム間を金線にて
ワイヤボンディング法により接続し、トランスファモー
ルド法にて樹脂封止した構造をもつトランスファモール
ド型の混成集積回路装置（ＣＯＭＰＡＣＴ）がある（例
えば、最新ハイブリッドテクノロジー、第２１５頁〜第
２１９頁、工業調査会、電子材料編集部、モールド型の
ハイブリッドＩＣ１第１回マイクロエレクトロニクスシ
ンポジウム論文集、ＩＳＩ−（Ｍ　　ＪＡＰＡＮ）。Conventionally, an insulating area is provided on a lead frame, a printed wiring board with predetermined wiring is pasted on top of the insulating area, and semiconductor elements, etc. are mounted as bare chips on predetermined positions on the printed wiring board. There is a transfer mold type hybrid integrated circuit device (COMPACT) which has a structure in which printed wiring boards and printed wiring boards and lead frames are connected using wire bonding method using gold wires and sealed with resin using transfer molding method ( For example, Latest Hybrid Technology, pp. 215-219, Kogyo Kenkyukai, Electronic Materials Editorial Department, Mold Type Hybrid IC 1 1st Microelectronics Symposium Proceedings, ISI-(M JAPAN).

（発明が解決しようとする課題〕 この従来の混成集積回路装置は、リードフレーム上にプ
リント配線基板を貼り付け、このプリント配線基板上に
所定の半導体素子をベアチップ状態にて搭載しているが
、リードフレームの下部へベアチップを搭載するのは困
難であるため、リードフレームの下部は、トランスファ
モールド封止された樹脂と接触する構造となっており、
混成集積回路装置の高集積化、高密度化を難しくしてい
るという問題点があった。(Problems to be Solved by the Invention) In this conventional hybrid integrated circuit device, a printed wiring board is pasted on a lead frame, and a predetermined semiconductor element is mounted in a bare chip state on this printed wiring board. Since it is difficult to mount a bare chip to the bottom of the lead frame, the bottom of the lead frame is designed to be in contact with the transfer molded resin.
There has been a problem in that it has been difficult to increase the integration and density of hybrid integrated circuit devices.

本発明のＩＩ的は、高集積化、高密度化が容易な混成集
積回路装置を提供することにある。A second aspect of the present invention is to provide a hybrid integrated circuit device that can easily be highly integrated and densely packed.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の混成集積回路装置は、少なくとも２つの半導体
ベアデツプを搭載したプリン１〜配線基板を片面に貼り
付けた第１のリードフレームと、少くとも２つの半導体
ベアチップを搭載したプリント配線基板を片面に貼り付
けた第２のリードフレームとを有し、前記第１のリード
フレーム面と前記第２のリードフレーム面とを接触さぜ
重ね合わぜて樹脂封止されている。The hybrid integrated circuit device of the present invention includes a first lead frame on which at least two semiconductor bare chips are mounted and a printed wiring board mounted on one side, and a printed wiring board on which at least two semiconductor bare chips are mounted on one side. A second lead frame is attached thereto, and the first lead frame surface and the second lead frame surface are brought into contact and overlapped with each other and sealed with resin.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.

第１図に示すように、リードフレーム１ａ上にプリント
配線基板２ａを貼り付け、プリント配線基板２ａ上に２
つの半導体ベアデツプ３ａをダイボンディングして搭載
し、さらに、金線４ａにてワイヤボンディングして、半
導体ベアチップ３ａとプリン１〜配線基板２ａ問および
プリント配線基板２ａとリードフレーム１ａ間を接続す
る。As shown in FIG. 1, a printed wiring board 2a is pasted on a lead frame 1a, and two
Two semiconductor bare depths 3a are mounted by die bonding, and further wire bonding is performed using gold wires 4a to connect the semiconductor bare chip 3a to the printed wiring boards 1 to 2a and between the printed wiring board 2a and the lead frame 1a.

一方、リードフレーム１ａ上にプリント配線基板２ｂを
貼り付け、プリント配線基板２ｂ上に２つの半導体ベア
チップ３ｂをダイボンディングして搭載し、さらに、金
線５ｂにてワイヤボンディングして半導体ベアチップ３
ｂとプリント配線基板２ｂ問およびプリント配線基板２
ｂとリードフレーム１ｂ間を接続する。On the other hand, a printed wiring board 2b is pasted on the lead frame 1a, two semiconductor bare chips 3b are mounted on the printed wiring board 2b by die bonding, and the semiconductor bare chips 3b are further wire bonded with gold wires 5b.
b and printed wiring board 2b and printed wiring board 2
b and lead frame 1b.

次に、フレーム１ａとリードフレーム１ｂをそれぞれプ
リント配線基板２ａ、２ｂを貼り付けていない面で重ね
合わせ、樹脂５をトランスファモールド法にて封止する
ことにより、本実施例の高密度で高集積された混成集積
回路装置が得られる。Next, the frame 1a and the lead frame 1b are overlapped with the surfaces to which the printed wiring boards 2a and 2b are not attached, and the resin 5 is sealed by a transfer molding method to achieve the high density and high integration of this embodiment. A hybrid integrated circuit device is obtained.

さらに、図示しないが、半導体ベアデツプ３ａの代わり
に、受動素子である表面実装部品タイプのチップコンデ
ンサを搭載することによっても高密度で高集積された混
成集積回路装置が得られる。Further, although not shown, a high-density and highly integrated hybrid integrated circuit device can also be obtained by mounting a surface-mount component type chip capacitor as a passive element in place of the semiconductor bare depth 3a.

〔発明の効果〕〔Effect of the invention〕

以−ト説明したように本発明は、リードフレームの上下
に半導体ベアデツプを搭載することにより、従来に比べ
て約２倍の高密度化、高集積化が可能となるという効果
を有する。As explained above, the present invention has the advantage that by mounting semiconductor bare depths above and below a lead frame, it is possible to achieve approximately twice the density and integration as compared to the conventional technology.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明の一実施例の断面図である。 ］、　ａ　、　　］、　ｔ：＋　＝−リードフレーム、
２ａ、２ｂ・−プリン１へ配線基板、３　ａ、　、　３
　ｂ・・・半導体ベアチップ、４ａ、、／１に＋・・金
線、５・・・樹脂。FIG. 1 is a sectional view of one embodiment of the present invention. ], a, ], t:+=-lead frame,
2a, 2b - Wiring board to printer 1, 3 a, , 3
b... Semiconductor bare chip, 4a, , /1 +... Gold wire, 5... Resin.

Claims (1)

【特許請求の範囲】[Claims] 　少なくとも２つの半導体ベアチップを搭載したプリン
ト配線基板を片面に貼り付けた第１のリードフレームと
、少くとも２つの半導体ベアチップを搭載したプリント
配線基板を片面に貼り付けた第２のリードフレームとを
有し、前記第１のリードフレーム面と前記第２のリード
フレーム面とを接触させ重ね合わせて樹脂封止したこと
を特徴とする混成集積回路装置。The first lead frame has a printed wiring board on which at least two semiconductor bare chips are mounted, and a second lead frame has a printed wiring board on which at least two semiconductor bare chips are mounted. A hybrid integrated circuit device characterized in that the first lead frame surface and the second lead frame surface are brought into contact with each other, overlapped, and sealed with resin.
JP2284898A 1990-10-23 1990-10-23 Hybrid integrated circuit device Expired - Lifetime JP2595803B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2284898A JP2595803B2 (en) 1990-10-23 1990-10-23 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2284898A JP2595803B2 (en) 1990-10-23 1990-10-23 Hybrid integrated circuit device

Publications (2)

Publication Number Publication Date
JPH04159765A true JPH04159765A (en) 1992-06-02
JP2595803B2 JP2595803B2 (en) 1997-04-02

Family

ID=17684478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2284898A Expired - Lifetime JP2595803B2 (en) 1990-10-23 1990-10-23 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JP2595803B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012057521A (en) * 2010-09-08 2012-03-22 Honda Motor Co Ltd Throttle device
KR101231296B1 (en) * 2006-09-25 2013-02-07 엘지이노텍 주식회사 Intelligent power module

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6028256A (en) * 1983-07-26 1985-02-13 Fujitsu Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6028256A (en) * 1983-07-26 1985-02-13 Fujitsu Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101231296B1 (en) * 2006-09-25 2013-02-07 엘지이노텍 주식회사 Intelligent power module
JP2012057521A (en) * 2010-09-08 2012-03-22 Honda Motor Co Ltd Throttle device

Also Published As

Publication number Publication date
JP2595803B2 (en) 1997-04-02

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