JPS6225794Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a reset circuit that operates when a microcomputer goes out of control.

Microcomputer (hereinafter referred to as microcomputer)
The program may run out of control due to a bug in the program, disturbance noise, etc., causing the program to fall into an infinite loop, or the stack to be destroyed and the program to jump to a completely unrelated address.

Conventionally, in order to prevent such a runaway of a microcomputer, an automatic reset circuit that detects runaway and resets the CPU has been installed as an accessory circuit.

The present invention provides an automatic reset circuit which has a simpler structure, is lower in cost, and has poor noise resistance.

The microcomputer reset circuit according to the present invention includes a detection circuit 9 that detects the presence or absence of the clear output signal A of the CPU 1, and two NAND function elements 1.
1 and 12 are connected in series, and the oscillation time constant circuit (resistance) returns from the connection point to the input of one element.
R ₃ , R ₄ , capacitor C ₂ ) and a Schmitt trigger feedback circuit (resistors R ₄ , R ₅ ) for feeding back from the output of the other element to the input of the one element. are doing.

The output of the detection circuit 9 is converted into two of the oscillation circuits 10.
The oscillation circuit 10 is controlled by applying the signal to the inputs of the two NAND function elements 11 and 12, respectively. Normally, a high level potential is transmitted from the oscillation circuit 10 to the CPU.
When the clear output signal is absent, the oscillation circuit 10 is activated and its oscillation output is applied to the reset input of the CPU 1.

This simple configuration allows the microcomputer to be automatically reset, and at the same time allows power-on reset.

The present invention will be explained below in comparison with the prior art.

FIG. 1 is a circuit diagram of a conventionally used automatic reset circuit, and FIG. 2 is a time chart showing its operation. In FIG. 1, a clear output terminal of a CPU (central processing unit) 1 outputs a clear signal (period t in FIG. 2A) that clears a program counter every time one program routine ends. This clear signal is given to the clear input CLR of the external counter 3 for the timer via the negative logic OR gate 2, so when the CPU 1 is operating normally, the counter 3 has a period of t.
The output _QD of the counter 3 will never reach the high level "H".

When the CPU 1 malfunctions and the program jumps into an infinite loop, and the clear signal CLR is no longer output as shown in Figure 2 A, the counter 3 counts the timer clock T-CK, and after a time T longer than the cycle t, the counter 3 counts the timer clock T-CK. _D output rises to H level. This output is given to the CR time constant circuit 5 via the inverter 4,
After being delayed by a minute time, it is fed back to the clear input of the counter 3 through the OR gate 2. Therefore, the Q _D output of the counter 3 returns to the low level "L", and as a result, the detection pulse shown in FIG. 2B is formed. This detection pulse represents that the CPU1 program has fallen into an infinite loop.

The detection pulse shown in FIG. 2B is converted into an L-level reset pulse shown in FIG. 2C through a Schmitt circuit 6 that prevents chatter during the reset operation.
This is applied to the reset input of the CPU 1, thereby resetting the CPU 1, and then returning the reset input to the H level to restart the CPU 1.

The automatic reset circuit shown in FIG. 1 requires a counter 3, a Schmitt circuit 6, etc., and also a generation circuit for the timer clock T-CK, resulting in a complicated circuit configuration and high cost. Also, when CPU1 is operating normally, the timer clock T-
There is also a risk that the CPU may malfunction due to electrical oscillation noise from the oscillator that generates CK. Furthermore, since the circuit of FIG. 1 does not have an automatic reset function when the system is powered on, a power-on reset circuit must be provided separately.

Next, FIG. 3 is a circuit diagram of an automatic reset circuit according to an embodiment of the present invention, and FIG. 4 is a time chart showing its operation. The reset circuit shown in FIG. 3 is composed of a detection circuit 9 and an oscillation circuit 10. CPU
1 is operating normally, the clear signal shown in FIG. 4A is output at a constant period t, as described above.

The clear signal is applied to the transistor Q ₁ of the detection circuit 9, turning this transistor Q ₁ on and off. The output of the transistor _Q1 is applied to the capacitor _C1 , and the capacitor _C1 is charged as shown in the section from d to e in FIG. 4B. Therefore d～e
In the normal operating range of , the terminal voltage of capacitor C ₁ is at a high level. The terminal voltage of capacitor C ₁ is applied to transistor Q ₂ via a voltage divider circuit consisting of resistors R ₁ and R ₂ to turn on transistor Q ₂ . Therefore, the output of transistor _Q2 is the fourth
As shown in Figure C, the level has become low.

The low level output of the transistor Q ₂ is given as an oscillation prohibition signal to the respective inputs of NAND gates 11 and 12 forming the oscillation circuit 10. These NAND gates 11 and 12 are coupled in series, and a time constant circuit consisting of resistors R ₃ and R ₄ and a capacitor C ₂ is provided between the input and output of the NAND gate 11, and operates as an astable multivibrator. . Additionally, a Schmitt trigger function is provided by feedback using a voltage divider circuit consisting of resistors _R4 and _R5 .

When the CPU 1 malfunctions and the program falls into an infinite loop, and the clear signal is no longer output as shown at times e to i in Figure 4A, the transistor _Q1 is turned off and the capacitor _C1 is turned off as shown in Figure 4B. As a result, transistor _Q2 is turned off as shown in FIG. 4C. As a result, the transistor
The output of _Q2 becomes high level, and the oscillation circuit 10 starts operating. Before the start of oscillation, capacitor C ₂ is positively charged by the high level outputs of NAND gates 11 and 12. When the inputs of the NAND gates 11 and 12 become high level at time f as shown in FIG. 4C, the inputs of the NAND gate 11 become (1, 1) and the output is inverted to a low level as shown in FIG. 4D. Therefore, the terminal voltage of capacitor C ₂ gradually decreases through resistor R ₃ .

Then, after a certain period of time T, the input of the NAND gate 11 becomes (1, 0), and the output becomes the point g in Fig. 4D.
to return to a high level. At this time, the input of the NAND gate 12 becomes (1, 1), and its output drops to a low level as at time g in FIG. 4E. The low level output of the NAND gate 12 is applied as a reset signal to the reset input of the CPU 1, and the CPU 1 is reset.

After the reset, the capacitor _C2 is charged with the high level output of the NAND gate _C2 , and its terminal voltage gradually rises, so after a certain period of time the input of the NAND gate 11 becomes (1, 1) and its output becomes The level becomes low again as at time h in FIG. 4D. As a result, the input of the NAND gate 12 is (1,
0), and its output becomes a high level as at time h in FIG. 4E. This high level output is applied to the reset input of CPU1, and CPU1 restarts.

After γ time after the CPU 1 is restarted, a clear signal is outputted as at time i in FIG. 4A, so the output of the detection circuit 9 is at time i in FIG. 4C.
The signal becomes a low level as shown in FIG. For this reason
The resistor is connected so that the period T of the low-level oscillation output of the oscillation circuit 10 is longer than the period γ from when the CPU restarts to when it issues the first clear signal.
Constants for R ₃ to R ₅ and capacitor C ₂ are determined.

Note that resistors R ₄ and R ₅ are used to give the oscillation circuit a Schmitt trigger effect.
When the level determined by R ₄ and R ₅ falls below the input threshold level of the NAND gate 11, the fourth
As at time g in Figures D and E, the output of the NAND gate 11 is inverted to high level, and the output of NAND gate 12 is inverted to low level. and nand gate 12
The low level output of is positively fed back to the input of NAND gate 1 through resistor _R5 . This shot trigger effect prevents glitches (chattering) in the reset signal and allows stable reset.

Next, the operation when the power switch is turned on at time a in FIG. 4 will be described. When the power is turned on, the power supply voltage rises at time b as shown in FIGS. 4A to 4D. At this time, the output of the detection circuit 10 is
The signal is kept at a high level as shown in FIG. C, and the oscillation circuit 10 operates. That is, the capacitor of the oscillation circuit 10
C ₂ is charged through resistor R ₆ with the high level output of NAND gate 11, and when one input of NAND gate 11 exceeds the threshold level after approximately T time, its output flips to a low level at time c. During this interval from power-on to time point c, the output of the NAND gate 12 is kept at a low level, thereby resetting the CPU 1. When the output of the NAND gate 12 becomes high level at time c, the CPU 1 starts, and a clear signal is outputted after γ time as shown in FIG. 4A. In response to this clear signal, the output of the detection circuit 9 becomes low level as shown at time d in FIG.
The operation of CPU 0 is stopped, and NAND gate 12 is closed to prohibit a new reset of CPU 1.

The present invention is constructed as described above, and includes a counter that detects the absence of a clear output signal, a clock generator that generates a clock for this counter, and a reset signal generated by the counter that prevents chatter. This eliminates the need for a Schmitt circuit or the like, and a low-cost reset circuit can be obtained with an extremely simple configuration. Furthermore, since it operates even when the power is turned on, it can also be used as a power-on reset circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventionally known automatic reset circuit for a microcomputer, FIG. 2 is a time chart showing the operation of FIG. 1, and FIG. 3 is a circuit diagram of an automatic reset circuit according to an embodiment of the present invention. FIG. 4 is a time chart showing the operation of FIG. 3. In addition, the symbols used in the drawings are 1...
CPU, 9...Detection circuit, 10...Oscillation circuit, 1
1, 12...Nand gate.

Claims (1)

[Claims for Utility Model Registration] A detection circuit that detects the presence or absence of a clear output signal of the CPU and two NAND function elements are connected in series,
Each of the oscillation circuits includes an oscillation time constant circuit that feeds back from the connection point to the input of one of the elements, and a Schmitt trigger feedback circuit that feeds back from the output of the other element to the input of the one element. , the output of the detection circuit is applied to the respective inputs of the two NAND functional elements of the oscillation circuit to control the oscillation circuit, and normally a high level potential is applied from the oscillation circuit to the reset input of the CPU; A reset circuit for a microcomputer configured such that when the clear output signal is absent, the oscillation circuit is activated and its oscillation output is applied to the reset input of the CPU.