JPS62260480A - Ccd reading method - Google Patents

Abstract

PURPOSE:To reduce a visually conspicuous fixed pattern noise by slashing a change in a signal area due to the jitter of a gate pulse supplied to a CCD read circuit. CONSTITUTION:By making a delay time 61 slightly shorter than a signal level period 60, a subtraction signal 50 is set to a zero level 62 or equal to a voltage at the time of closing a gate means when the operation is around the rise or fall of a gate pulse 45(during a period 59 including a timing jitter). Accordingly, if the timing jitter is present, it never affects a signal output, and a visible noise showing up as a periodical longitudinal stripe can be removed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a CCDCCD image pickup device number readout method, and in particular, to noise generated by a floating diffusion amplifier (FDA) incorporated in the image pickup device and the output It reads out video signals with low noise without being affected by the reset noise that occurs when resetting the diode, and also reduces the effects of timing jitter in the image sensor drive circuit, reducing random noise and fixed pattern noise. .

[Prior art] A correlated double sampling method has traditionally been used to remove reset noise, but since the noise generated by the FDA has no correlation with the signal, low frequency components are removed, but high Frequency components remain without being removed.Also, attempts have been made to reduce the high frequency components of noise by limiting the frequency characteristics of the FDA, but since sample and hold is performed in the subsequent stage, it is difficult to lower the band too much. It is not possible to achieve sufficiently low noise.

FIG. 4 shows an example of a conventionally used correlated double sampling circuit. Here, 100 is a CCD element, 1 and 2 are amplifiers, 3 is a differential amplifier, 4 to 7 are capacitors, 8 to 10 are analog switches, 11.12 is a driver that drives switches 8, 9, and 10, respectively; is the CCD readout output taken out from the amplifier 3.

Here, as shown in FIG. 5, the feedthrough level 40 of the output of the CCD element 100 is sampled and held by the switch 8 and the capacitor 5, and the signal level 41 of the output of the CCD element 100 is sampled and held by the switch 9 and the capacitor 6.
Sample and hold.

When the reset switch in the CCD element 100 is on, the output shows a reset level 42, and when the reset switch is off, it shows a feedthrough level 40. In this case, reset noise is superimposed on the signal output. After this,
In the CCD element 100, the signal charge is transferred from the transfer section to the output diode, thereby indicating a signal level of 41. Since no noise is generated at this time, reset noise of exactly the same value is superimposed. Therefore, the differential amplifier 3
The conventional correlated double sampling method removes reset noise by taking the difference between the signal level 41 and the feedthrough level 40 stored in the capacitors 6 and 5, respectively.

There are two possible methods for this: one is to sample and hold both the signal level and the feedthrough level and take the difference, as shown in Figure 4, and the other is to clamp the feedthrough level and take the difference equivalently. Both are considered to be equivalent in principle. In this clamping method, when the internal amplifier has a lot of noise as in the case of a CCD image sensor, the amplifier noise is held or clamped, and the effect of removing the reset noise υ is small.

In order to remove such amplifier noise, conventionally the sixth
A circuit like the one shown in the figure was used. FIG. 6 shows the sample and hold circuit part, where 14 is an input, 15 is an output, 1B and 17 are amplifiers, 18 is a capacitor,
19 is an analog switch, 20 is a resistor, 21 is a control signal, and 22 is an amplifier.

Sample and hold is performed using the switch 19 and the hold capacitor 18. At this time, the on-resistance of the switch 19, the resistance component of the external resistor 20, and the time constant of the capacitor 18 provide a filter effect and remove the above-mentioned amplifier noise. It is possible to do so.

As for this filter effect, the longer the time constant, the more effective it is at removing noise, but on the other hand, if the time constant is too long, it becomes difficult to distinguish between the feedthrough level and the signal level, and the reset noise removal effect is lost. There is this inconvenience.

[Problem to be solved by the invention] Therefore, by using an analog delay line to take the difference between the signal level and the feedthrough level in advance and extracting only the section where the difference is correctly taken, the low frequency It is conceivable to remove the high-frequency noise generated by the floating diffusion amplifier (F[lA) in the CCD by removing the reset noise and passing the output through a low-pass filter. That is, a delay means for delaying the output of the CCN image sensor by a predetermined time, a means for subtracting between the signal delayed by the delay means and the output of the CCD image sensor; A means for extracting a signal component in a superimposed period of a signal level period and a feed-through level period of a delayed signal, and among the extracted signal components, a component corresponding to a signal bandwidth of a CCD image sensor is passed through to obtain an imaged signal. It is possible to construct a CCD readout circuit including filter means for extracting the information.

Regarding such a CCD readout circuit, the present applicant has already filed an application (Utility Model Application No. 80-30318), but since the application has not yet been published, a more detailed explanation will be provided.

FIG. 1 shows the overall configuration of the above-described CCD readout circuit, where 30 is a CCD element including an FDA. 3
2 is a buffer amplifier supplied with the CCD output 43 via a capacitor 31; 33 is a delay line supplied with the output of the amplifier 32; 34 is a differential amplifier that subtracts the output of the amplifier 32 from the output of the delay line 33, and 35 is a differential amplifier that supplies the output of the differential amplifier 34 via a gate means composed of a resistor 38 and a switch 37. 37 is a differential amplifier 3.
38 is a buffer amplifier supplied with the output of the switch 37, and 39 is the CCD read output taken out from the buffer amplifier 3B.

A CCD output signal 43 obtained by the buffer amplifier 32 under an output impedance of an appropriate magnitude is delayed by a delay line 33, for example, by a feed-through level period. Furthermore, both signals 43 and 44 are
After taking the difference from In this case, when the output of the amplifier 34 is taken out, if the delay time of the delay circuit is selected so that the overlap between these periods is maximized, the time width of the gate output signal can be increased, which is advantageous in terms of signal processing.

Note that in this example, the resistor 3B and the switch 37 are used, but a multiplier circuit may be used instead.

By passing the gate output 46 described above through a predetermined low-pass filter 35 via a buffer amplifier 38, spike noise (high-frequency noise) can be removed, and a CCD readout output 39 from which FDA low-frequency noise has also been removed is obtained. . That is, the CCD output signal 43 includes low-frequency and high-frequency noise in both its feed-through level and signal level, but the low-frequency noise is removed as the gate output 4B, and the high-frequency noise is removed as the gate output 4B. Noise and harmonics associated with the gate are removed by the low-pass filter 35.

However, as is clear from the timing diagram shown in FIG. 3, since the subtraction signal 50 has a large level change (or even if the level is constant, it is not zero but a large value), the gate pulse 45 Even a slight change 58 in timing will manifest itself as a fluctuation in the signal output.

In this way, when there is timing jitter in the gate pulse or CCD drive pulse, the gate pulse width effectively changes, causing fixed pattern noise, and even the slightest jitter becomes noticeable. Timing jitter is caused by periodic waveform changes due to the influence of the frequency divider circuit in the drive circuit, pulse width changes due to threshold fluctuations in the waveform shaping circuit, etc., and it is extremely difficult to eliminate such jitter. It is difficult to

[9. OBJECT OF MARK] Therefore, in view of the above-mentioned points, an object of the present invention is to reduce changes in signal area caused by jitter of gate pulses supplied to a CCD readout circuit, thereby eliminating visually noticeable fixed pattern noise. The objective is to provide a method to reduce

[Means for Solving the Problems 1] In order to achieve the above object, the CCD reading method according to the present invention includes a reset level period.

Delay means for delaying the output of the CCD image sensor that repeatedly occurs in the order of the feed-through level period and the signal level period by a predetermined time; and means for subtracting between the signal delayed by the delay means and the output of the CCD image sensor. a gate means for extracting, from the subtracted output, a signal component in a superimposed period of the signal level period of the output of the CCD image sensor and the feed-through level period of the delayed signal; and filter means for extracting the image signal by passing a component corresponding to the signal bandwidth of the image sensor, and when the delay time of the delay means is shorter than the feed-through period and the signal period. 111 width to form a period in which the signal level of the subtraction output is zero, and a signal component of the superimposed period is extracted including a part of the formed period in which the signal level is zero.

【Example] Hereinafter, the present invention will be described in detail based on Examples.

As an embodiment of the present invention, the CCD shown in the first diagram described above is used.
Uses a readout circuit. Therefore, since each component is as already described, a description thereof will be omitted.

FIG. 2 is a timing diagram illustrating the operation of this embodiment. The operation of this embodiment will become clear by comparing it with the timing diagram shown in FIG. 3 described above. That is, the delay time 61 is made slightly shorter than the signal level period 60, and the subtraction signal 50 is always at the zero level 62 or near the rise and fall of the gate pulse 45 (at least in the period 59 with timing jitter). , the voltage is made equal to the voltage when the gate means is closed. As a result, even when there is timing jitter, it does not affect the signal output.

[Effects of the Invention] By carrying out the present invention, (a) The conventional disadvantage that a slight error in the phase of the sampling pulse or gate pulse causes radio wave interference, which becomes noticeable as a beat M shape of the drive signal. can be resolved.

(α) Visual noise that appears as periodic vertical stripes can be removed by jumping in from the frequency dividing circuit in the drive circuit.

(c) It is possible to prevent changes in characteristics due to changes in temperature or changes in the phase of pulses when the power is turned on.

Thus, in the present invention, there is no need to strictly provide a shield or a ground line for removing these visual noises, so it is possible to realize a lightweight and inexpensive imaging device.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of a ccn readout circuit used to implement the present invention. FIGS. 2(A) to ([3)] are timing diagrams showing the operation of the embodiment shown in FIG. 1, and FIGS. 3(A) to (D) explain inconveniences caused by not implementing the present invention. Timing diagram. Figure 4 is a circuit diagram showing a conventional correlated double sampling circuit. Figures 5 (A) to (E) are signal waveform diagrams showing the operation of Figure 4. Figure 6 is a general sample hold. FIG. 2 is a circuit diagram showing a circuit. 30... CCD element, 31... Capacitor, 32... Buffer amplifier, 33... Delay line, 34... Differential amplifier. 35...Low pass filter, 36...Resistor, 37...Switch, 38...Buffer amplifier. Figure 4, 6th picture

Claims (1)

[Scope of Claims] Delay means for delaying the output of a CCD image sensor that repeatedly occurs in the order of a reset level period, a feed-through level period, and a signal level period by a predetermined time; and a signal delayed by the delay means and the CCD. means for subtracting the output from the image sensor output; and gate means for extracting a signal component of the signal level period of the CCD image sensor output and the feed-through level period of the delayed signal from the subtracted output. , Out of the extracted signal components, the component corresponding to the signal bandwidth of the CCD image sensor is passed through a circuit including a filter means for extracting an image signal, and the delay time of the delay means is set to the feed signal. Set to a time width shorter than the through period and the signal period to form a period in which the signal level of the subtracted output is zero, and the signal of the superimposition period including a part of the formed period in which the signal level is zero. A CCD reading method characterized by extracting components.