JPS62272296A - Color liquid crystal display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] The present invention relates to a liquid crystal display panel with a matrix structure,
R (red), G (green), and B (blue) pixels arranged on the X-direction line of the panel are arranged in the same order.

It is driven by a data line driver circuit that simultaneously operates a plurality of sampling switches for writing video signals in correspondence with the l-bi-node shift data signal of the shift register of the data line driver.

[Industrial application field]

The present invention relates to a color liquid crystal display device having a matrix configuration display panel.

Since such a liquid crystal display panel can easily be colored by combining a color filter with the panel, a small-sized color liquid crystal display device for displaying characters and images (television) using the same is being considered.

The present invention improves the quality of characters displayed on a panel, and also improves the quality of characters displayed on a panel.
This was done in response to a request to simplify the data line driver circuit that performs signal control (color).

[Conventional technology]

Figure 4 shows the pixel configuration of a display panel that arranges R, G, and B pixels, and an example of displaying characters using any of R, G, or B using this configuration (the figure shows A, B, and C from the left). , K) are shown.

In Figure 4 ■, the pixel arrangement of R, G, and 8 pixels is an L-type mosaic; the pixel arrays of ■ and ■ are inline type of R, G, and 8 pixels; This is the case with panels.

FIG. 5 is a driving circuit diagram of an L-shaped mosaic array panel.

and FIG. 6 is a driving circuit diagram of an in-line type array panel.

The basic circuit configuration and its operation outline will be explained according to the diagram.

When driving the panel, a scanning line driver that performs display scanning in units of 9 rows and a data line driver that performs write sampling are provided, and the scanning line driver and data line driver are driven by timing pulses from a common synchronous control circuit. Ru.

In both figures, 21 is a synchronization control circuit in both vertical and horizontal directions.

Reference numeral 22 is a scan driver that sequentially scans each horizontal line of the panel 19 (or 20), and 23 and 24 are both data line drivers that input display write data to vertical lines.

The data line driver 23 or 24 is connected to the shift register 25 . Sampling switch 26. Sampling capacitor 27. and a buffer driver 28.

The shift register 25 sequentially shifts the data signal input from the shift data input terminal 30 to the right using a shift clock from the clock terminal 31. The data signal from the terminal 30 is a 1-bit high level signal in the shift register, and the high level is sequentially moved by the shift clock.

Each bit of the shift register 25 is output to the control line 32 of the gate G of the sampling switch 26 (FET element), and when a high level signal of the shift data is output, the corresponding source S of the sampling switch 26 is output. The drain D is turned on.

At this time, R, G, B switch 7g circuit 29 (7) VID
l, video input terminals 33 for VID2 and VID3 respectively
When R, G, and B display signals are input to
After the display signal for the scanning line is input to the sampling capacitor, the buffer driver 28 writes the display to the panel. This display is performed for all pixels arranged in the X direction of the panel.

The display panel 19 in FIG. 5 has an in-line (mosaic) pixel configuration corresponding to column 3 in FIG.

For example, when A, B, C, and K are displayed, the visibility of the display is poor due to character distortion due to the irregular arrangement of pixels (dots).

Furthermore, the panel 20 in Fig. 6 corresponds to Fig. 4 (■) in which the basic circuit configuration is the same as that in Fig. 5, but the two-pixel arrangement is an inline type (stripe) configuration, and the table in the column (■) in the same figure corresponds to the case. The visibility is excellent when compared to the example shown.

[Problem that the invention seeks to solve]

As seen in the driving method for R, G, and 8 pixels explained in FIGS. 5 and 6, the circuit configuration of the conventional data line driver consists of dots arranged in the
The bits correspond to 1=1, and are sent sequentially every time the shift register sends 1 bit.

Since display data is sampled, for example, when driving a large-area display panel 19 or panel 20 with a large number of pixels, the clock frequency of the shift operation increases, and as a result, the data line driver 2 having an IC configuration increases.
3 or 24 requires high-speed operation.

Furthermore, as the clock frequency increases, problems arise, such as the time required to write data to the sampling capacitor 27 becomes shorter.

[Means for solving problems]

R, in response to the shift signals of the scanning line driver 22 and the shift register 25 which is sequentially shifted by the shift clock.
A data line driver 23 for sampling G and B video signals. In a display panel 2o that has a set of (R, G, B) pixels arranged in a matrix.

For all scanning lines, - sets of (R, G, B) pixels 10 are arranged in the same order, and for one bit of the shift register 25, signals from the R, G, B video input terminals 30 are arranged. The above-mentioned problem is solved by providing the color liquid crystal display device of the present invention, which includes data line drivers 11 and 12 (or 13 and 14) that simultaneously operate two or more sampling switches 16 for sampling signals. (See Figure 1 or Figure 2).

[For production]

Since it is an inline configuration in which a set of R, G, and B pixels are arranged in the same order for all scanning lines, when displaying one character, the character is not blurred and the display quality is improved compared to a mosaic pixel arrangement. Are better. In addition, since multiple sampling switches operate simultaneously for one bit of the shift register of the data driver, the operating frequency of the shift register can be reduced compared to the conventional configuration (1:1), reducing the cost of the data line driver. Lower power consumption is achieved.

〔Example〕

An embodiment of the configuration of a drive circuit for a display panel of the present invention will be described with reference to FIGS. 1 and 2. FIG. In the drawings, panel drive circuit elements that are the same as those of the prior art are given the same reference numerals.

In FIG. 1 or 2, the arrangement configuration of a set of R, G, and B pixels 10 combined with a liquid crystal display panel is an in-line type.

In both figures, the R, G, and B pixels 10 preferably have an aspect ratio of 1:1 as shown in FIG.

In the configuration of the data line drivers 11 and 12 shown in FIG. control at the same time.

Three sampling switches 16 for simultaneous sampling are connected to video signal lines input corresponding to the R, G, and B pixels 10, respectively.

Therefore, if the 1-bit signal is at a high level.

The three sampling switches 16 operate, and depending on the presence or absence of signal input from the corresponding video signal terminal 33, R and G are selected.

B It will be displayed in any color.

That is, the drain D side of the FET element 18 is connected to the video input terminal 33, and the source S side of the element 18 is connected to the sampling signal.
A shift register 25 is connected to the gate G side of the element 18.
A write bit signal line 32 is connected thereto.

Therefore, the sampling operation clock for data writing by the shift register only needs to operate once for three dots, and the operating frequency for driving R, G, and B pixels by the data line drivers 11 and 12 is lower than that of the conventional one. A third is fine.

The embodiment shown in FIG. 2 is a side view of a circuit in which each data line is divided into upper and lower drivers 13 and 14 to drive the line.

Both data line drivers 13 and 14 are examples in which two sampling switches 17 are provided that are simultaneously driven in response to the 1-bit output signal from the shift register 25.

The data line driver configuration circuit of FIG. 2 includes a sysampling capacitor 27. The configurations of the buffer driver 28 and the like are the same as in FIG.

In FIG. 2, the operating frequency for driving R, G, and B pixels in an in-line arrangement by the data line drivers 13 and 14 is two-thirds that of the conventional circuit configuration.

〔Effect of the invention〕

As is clear from the above description, according to the color liquid crystal display device of the present invention, the R, G, and B pixel arrays of the panel are arranged in an in-line type.

This has the advantage that a panel with good practical performance can be realized at low cost, such as by simplifying the data line driver circuit for driving the panel display and by improving the visibility of the two-character display.

[Brief explanation of the drawing]

FIG. 1 is an embodiment of the circuit configuration of the display panel of the present invention. FIG. 2 is a diagram showing another embodiment of the circuit configuration of the display panel of the present invention. FIG. 3 shows the aspect ratio of the pixel according to the example. FIG. 4 is a diagram explaining the color pixel array configuration and character display quality. 5 and 6 are circuit configuration diagrams of conventional display panels. In the figure, 10 is a set of (R, G, B) pixels. 11. 12, 13, 14. 23 and 24 are data line drivers. 16, 17 and 26 are sampling switches. 18 is a FET (switch) element. 19 and 20 are display panels.

Claims (2)

[Claims] (1) R, G in response to the scan line driver and the shift signal of the shift register that shifts sequentially using the shift clock.
, and a data line driver that samples video signals of B) in the same order, and a data line driver that simultaneously operates two or more sampling switches that sample R, G, and B video signals for one bit of the shift register. Color liquid crystal display device. (2) The color liquid crystal display device according to claim 1, wherein three sampling switches corresponding to pixels R, G, and B are operated simultaneously.