JPS6227435B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a character position detection device used in a character position detection section of an optical character reading device.

Forms that can be handled by general optical character reading devices have a predetermined position (character area) where characters are written, and the area around that area is a clear area where nothing is written in a color other than the dropout color. limited to. Therefore, in general optical character reading devices used for such forms, it is not necessary to add a special device to detect character positions.

However, with a special optical character reading device, there are cases where it is necessary to read characters on a document whose character area is not defined. For example, this applies to reading the address display on mail. The position of the postal code on mail items is not constant, except for postcards with a red frame and envelopes with a designated display position. In particular, the position of the postal code stamped on the mail along with the address using a typewriter or line printer is completely uncertain. Conventionally, with postal code reading devices that handle this type of mail, it has been necessary for a person to tell the reader the approximate location of the postal code each time the reader wants the reading device to read the postal item. . This method can be sufficiently effective in places where a large number of mail items of the same type are brought in and processed, but in places where various types of mail items are handled, this method is difficult to process by the reading device. The speed will be significantly reduced and the benefits of mechanizing the process will be lost.

The purpose of this invention is to solve this conventional difficulty,
Provided is a character position detection device that uses a new method to automatically locate locations where characters are likely to be written on a form with an undefined character area at high speed and with relative accuracy. It's about doing.

The character position detection device according to the present invention includes means for sequentially extracting one row or one column of binary quantized image signals from an image, a black image portion having a certain width or less, and a white image portion having a certain width or less in the one row or one column. and a means for detecting that a certain number or more are alternately present.

When one row or column in which the characters of this invention are written is scanned in a straight line that crosses all the written characters, the output of the scanning section is a short black image signal and a short white image signal alternately. The phenomenon of multiple occurrences is used. When a figure other than a character is scanned, a long black image signal or a long white image signal is often included in the middle, and it is possible to distinguish most images into figures and characters using this method.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The character position detection device of the present invention will be described in detail below based on embodiments thereof using the drawings.

The structure of an embodiment of the present invention is shown in a block diagram in FIG. The entire document is scanned by the scanning device 1 and stored in the storage device 2 as a binary quantized image signal in which black pixels are set to 1 and white pixels are set to 0. An example of an image stored in the storage device 2 is an arithmetic numeral as shown in FIG. The purpose of the character position detection device of the present invention is not to recognize characters, but to detect the positions where characters exist as images. Therefore, with the character position detection device of the present invention, it is also possible to scan with wide intervals in the row or column direction, and when such scanning is performed, if the image is a character, the shape will be similar to the original shape. It becomes so distorted that it cannot be fixed.

The binary quantized image signal thus stored in the storage device 2 is sequentially transferred to the shift register 3 as a binary signal corresponding to each pixel row by row or column by column from a predetermined position. A subsequent circuit determines whether a character portion is included in the image signal. In this case, as shown by the dotted line in FIG.
It is also possible to directly transfer the quantized image signals, which are binarized corresponding to each pixel row by row or column by column from a predetermined position of the image, to the shift register 3.

The quantized image signal stored in the shift register 3 is sequentially shifted according to the length of the figure using the clock 1 as a shift pulse. Clocks 1, 2, 3 and 4 in FIG. 1 are generated repeatedly at equal intervals for each pixel transmission time, as shown in FIG. 3.
For example, it is assumed that in the quantized image signal transferred and stored in the shift register 3, black pixels or white pixels are generated in the order of 1, 2, . Two terminals t ₁ and t ₂ are provided at the final stage of the shift register 3, and when the output corresponds to a black pixel, the logic value of the signal at the black pixel output terminal t ₁ is “1” and the signal at the white pixel output terminal t ₂ The logical value of this signal becomes "0", and the logical value of this signal is reversed when outputting corresponding to a white pixel. The black pixel output terminal _t1 of the shift register 3 is connected to the data input terminal D of the 1-bit register 4 and to one of the input terminals of the NAND gate 6. Further, the white pixel output terminal _t2 of the shift register 3 is connected to one of the input terminals of the NAND gate 5. The black pixel output terminal t ₃ of the 1-bit register 4 is connected to the other input terminal of this NAND gate 5, and the white pixel output terminal t ₄ is connected to the other input terminal of the NAND gate 6. Data is read into the shift register 4 using the clock 1.

Therefore, the information PATL from the black pixel output terminal _t1 of the shift register 3 is sent to the 1-bit register 4 as the third
As shown in FIG. 3, each output terminal PATR is applied in synchronization with the falling edge of clock 1.
It is set as shown below. When the logical value of the output of the white pixel output terminal _t2 of the shift register 3 is "1", and the logical value of the output of the black pixel output terminal _t1 of the register 4 is "1", the logical value of the output of the NAND gate 5 is "1". 0”. This state is as shown in FIG. 3. This state indicates that there is a change from black to white in the pixels of the image. In addition, when the logic value of the output of the black pixel output terminal _t1 of the shift register 3 is "1" and the logic value of the output of the white pixel output terminal _t2 of the register 4 is "1", the NAND gate 6 changes the logic of the output. The value becomes “0”. This state is as shown in FIG. 3, indicating that there is a change from white to black in the pixels of the image.

The output terminals of the NAND gates 5 and 6 are respectively connected to the input terminals of the NAND gate 20, the output terminal of the NAND gate 20 is connected to one of the input terminals of the NAND gate 21, and the clock 4 is applied to the other input terminals. There is. The output terminal of this NAND gate 21 is connected to one of the input terminals of the NAND gate 7, and the inverted signal of the initialization signal INIT is applied to the other input terminals, and the output signal is used as a reset signal. Therefore, as shown in FIG. 3, the reset signal is activated in synchronization with clock 4 during initialization and when there is a change from a white pixel to a black pixel or from a black pixel to a white pixel in one column or row of pixels. Emitted.

A counter 8 is provided, and when the logical value of the output of the black pixel output terminal _t3 of the register 4 is "1", this counter counts up in synchronization with the clock 2 as shown in FIG. When a predetermined value, for example 8, is reached, the count-up is stopped. This counter 8 is used to check whether the width of the black image portion is 8 meshes (pixels) or more. On the other hand, a counter 9 is provided, and this counter 9 counts up in synchronization with the clock 2 as shown in FIG. 3 when the logical value of the output of the white pixel output terminal _t4 of the register 4 is "1". When the content reaches a predetermined value, for example 6, the count-up is stopped. This counter 9 is used to check whether the width of the white image portion is 6 meshes or more.

The counters 8 and 9 are configured to be cleared by a reset signal output from the NAND gate 7. As mentioned above, the NAND gate 7 detects a change from a white pixel to a black pixel or from a black pixel to a white pixel at the time of initialization, and when the clock 4
It is configured to output output when it occurs. One of the input terminals of a NAND gate 12 is connected to the _QD output terminal, which obtains an output when the counter 8 counts a predetermined value 8, via a negative circuit, and the output terminal of the NAND gate 5 is connected to the other input terminals of the NAND gate 12, respectively. signal and clock 3 are provided as input signals. In addition, the output terminal of the AND gate, which has the Q _B output terminal and the Q _C output terminal, which provide output when counting the counters 9 and 4, respectively, are connected to their respective input terminals, is connected to one of the input terminals of the NAND gate 13 through a negative circuit. connected to. The output signal of the NAND gate 6 and the clock 3 are respectively applied to other input terminals of the NAND gate 13 as input signals. The output terminals of the NAND gates 12 and 13 are connected to respective input terminals of the NAND gate 23, and the output terminals thereof are connected to the input terminals of the counter 10.

Therefore, when the NAND gate 12 changes from a black pixel to a white pixel, if the content of the counter 8 is 7 or less,
A count-up output of the counter 10 is generated in synchronization with the clock 3 as shown in FIG. 10. Similarly, when the content of the counter 9 is less than 5 when a white pixel changes to a black pixel, the NAND gate 13 generates a count-up output of the counter 10 in synchronization with the clock 3 as shown in FIG. .
A NAND gate 14 connected to the clear terminal of the counter 10 causes the counter 10 to pass when the content of the counter 8 reaches 8 and when the content of the counter 9 reaches 6.
A character confirmation signal LET is output from , and an output is output to clear the counter 10 when clock 1 is generated and at initialization. The Q _A output terminal and Q _C output terminal of the counter 10 are connected to the input terminal of an AND gate 11, and the character confirmation signal is obtained at the output terminal of the AND gate 11.

Therefore, this counter 10 is a counter for checking whether black pixels whose width is 7 meshes or less and white pixels whose width is 5 meshes or less have appeared alternately and consecutively for a total of 5 times. gate 1
1 outputs a character confirmation signal LET indicating "character exists" as shown in FIG. 311. On the other hand, the counter 15 counts the number of shifts in the shift register 3, is cleared at initialization, and is counted up at clock 1. Memory 17 is the counter 1 when the character confirmation signal LET is output.
It memorizes the contents of 5, and the character confirmation signal LET
counter 15 in synchronization with clock 4 when
The contents of are written. The address of the memory 17 is determined by the counter 16, but the counter 16 is cleared at initialization and receives the character confirmation signal.
When there is LET, the count is increased in synchronization with the fall of clock 4 as shown in FIG. 3.

When the shift of one row or one column of figures stored in the shift register 3 is completed, the counter 16 stores the number of times the character confirmation signal LET is generated, and the memory 17 stores the number of shifts at that time. Character position is counter 16 and memory 17
It is determined from the contents of , and the position of one row or one column set in the shift register 3.

As is clear from the detailed explanation above,
By using the character position detection device of the present invention, it becomes possible to automatically detect character positions on a form with an undefined character area at high speed and with relative certainty. For items whose character positions have been automatically detected in this way, for example, the postal code of the item can be automatically read, and the item can be automatically processed. Although the character position detection device of this invention is not capable of detecting 100% character positions, it is possible to perform automatic processing as described above for detected character positions, and for those that cannot be detected, manual processing is performed as in the conventional method. . Furthermore, the character position detection device of the present invention has a simple structure and can reduce manufacturing costs compared to conventional devices. It is clear that by appropriately selecting the setting values of the counters shown in the block diagram of FIG. 1, the position of not only characters but also graphics can be detected in the same manner with the apparatus according to the present invention.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the character position detection device of this invention, FIG. 2 is an example of an input figure handled in the embodiment of the character position detection device of this invention, and FIG. FIG. 3 is a signal waveform diagram at each part of the embodiment. 1: Scanning device, 2: Storage device, 3: Shift register, 4: Register, 8, 9, 10, 15, 1
6: Counter, 17: Memory.

Claims (1)

[Claims] 1. A means for sequentially extracting one row or one column of pixels constituting an image as a binary quantized image signal corresponding to the pixel, and a fixed number of consecutive pixels in one row or one column of binary quantized image signals extracted by the means. A character position detection device comprising means for detecting that a black image portion consisting of the following black pixels and a white image portion consisting of a certain number or less of white pixels are alternately present in a certain number or more.