JPS6230114Y2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a line width detection circuit that can accurately detect the line width of a read image.

In an optical reading device or the like, a method of binarizing a video signal read by a photoelectric element, converting it into a digital signal, and inputting the digital signal to a computer or the like is a commonly used method.

In this case, in order to accurately know the line width of the target figure shown in the read image, it is necessary to accurately detect the signal width of a binarized signal obtained by faithfully binarizing the video signal.

Usually, the detected line width is obtained as a value counted by a count clock only during logic "1" of the binary signal (a certain portion of the signal is described as logic "1"). In this case, when the reading photoelectric element is a self-scanning photoelectric element (for example, a CCD element), the scanning clock of the element serving as the reference of the coordinate system of the reading device is used as the count clock. This is because one pulse of the scanning clock corresponds to one bit of the self-scanning photoelectric element, so it is possible to determine in real time how many bits of the photoelectric element there are line signals, etc. by counting the scanning clocks in between. This is because it is necessary to obtain the signal width in correspondence with the scanning clock in this way in order to obtain the line width for how many bits of the photoelectric element.

By the way, the phase relationship between the binary signal and the count clock is not necessarily constant, so if you count a binary signal with the same width using the count clock, you will get different values depending on the phase relationship. .

For example, in Fig. 1, it is a count clock, and , is a binary signal of the same width,
Since the phase relationship with the count clock is different, a signal width of 3 clocks and 2 clocks is obtained for the signal, which has the disadvantage that the signal width of the binary signal cannot be accurately measured.

This is particularly noticeable when the reading photoelectric element is not of the self-scanning type as described above.

In other words, in a reading device that uses a non-scanning type device such as a photodiode as a reading photoelectric element and sequentially receives images read by a scanning optical system, the coordinate reference of this device is This is because there is a possibility that the phase relationship between the clock corresponding to the above-mentioned scanning clock and the binary signal of the signal from the photodiode may be significantly shifted.

One possible solution to this problem is to measure the line width using a clock with a higher frequency than the clock that serves as the coordinate reference, and then transform the determined line width into coordinates, but this would not allow line widths to be obtained in real time. do not have.

The present invention aims to solve these drawbacks and provides a circuit that can accurately measure the signal width of a binary signal using a scanning clock in real time.

Hereinafter, details of the present invention will be explained according to examples.

FIG. 2 is a circuit diagram showing an embodiment of the present invention.

In the figure, a is an interpolation clock, and the frequency of the interpolation clock a is divided by a frequency divider 1 to obtain a scanning clock b serving as a coordinate reference. On the other hand, c is a binary signal, and in this example, the signal width when the logic is "1" is detected.

This binary signal c is inverted by a NOT circuit 5, and ANDed with an interpolation clock a by an AND circuit 6. Then, only when there is no binary signal c (logic "0"), the interpolation clock d is sent to the output of the AND circuit 6.
is obtained and led to the subtraction counter 2.

Now, in this example, assuming that frequency divider 1 is a 1/5 frequency divider, subtraction counter 2 constitutes a quinary subtraction counter, and for each input of interpolation clock d, 4, 3, 2,
This is a subtraction count such as 1, 0, 4, 3, etc. On the other hand, 3 is a storage circuit such as a flip-flop, which is set at the rising edge of the binary signal c.
It is constructed so that it is reset by the zero output e of the subtraction counter 2.

Figure 3 shows a time chart for each part.

Continuing the explanation while referring to Fig. 3, Fig. 3 a is an interpolation clock, b is a scanning clock that counts the binary signal width, and the frequency of the interpolation clock a is divided by one-fifth. It is something. c is a binary signal whose purpose is to detect the width between logical "1"s.

While the binary signal c is logic "0", the interpolation clock d is outputted to the output of the AND circuit 6 and inputted to the subtraction counter 2, so the subtraction counter 2 is 4,
Subtraction counting is performed in the order of 3, 2, 1, 0, 4, 3, . . . , and when the count value is 0, a zero output e is obtained.

Now, when the binary signal c becomes logic "1", at that point the interpolation clock d is no longer output to the output of the AND circuit 6, and the count value of the subtraction counter 2 changes to the previous value. During logic “1”,
It will be preserved. The count value in this case is as shown in FIG. This held count value represents the number of interpolation clocks from the rising edge of the binary signal c to the next basic clock.

On the other hand, the storage circuit 3 is set at the rising edge of the binary signal c. Next, when the binary signal c disappears (becomes logic "0"), the interpolation clock d is output again to the output of the AND circuit 6, and subtraction counting is started. When the subtraction counter reaches zero, a zero output e is output and the memory circuit 3 is reset. Memory circuit 3
The output h is shown in Fig. 3h.

In order to equalize the relationship between the values of the interpolation clock and the subtraction counter, it is sufficient to preset the subtraction counter to 4 using the AND output g from the AND circuit 7 between the output of the storage circuit 3 and the scanning clock b.

The relationship between the binary signal c and the Q output of the storage circuit 3 is such that the number of interpolation clocks between the rising edge of the binary signal c and the next scan clock
It is related to the extended trailing edge of . If the AND circuit 4 takes the AND of the Q output of the memory circuit 3 and the scanning clock b, the output clock f becomes the number of clocks indicating the binarized signal width, and by counting this clock f, the signal This will give you an accurate width value. Here, we have explained the case where a subtraction counter is used, but this applies to 0, 1, 2, 3, 4,
The same thing applies to an addition counter that counts 0, 1, 2, . . . , and in this case, it is sufficient to output 4 instead of the zero output e.

Also, instead of the preset of 4 using the basic clock, it is necessary to clear it to zero. If the frequency of the interpolation clock is increased relative to the frequency of the scan clock, even more accurate values can be measured with the base clock.

Since the present invention is configured as described above, it is possible to obtain the number of clocks with an accurate width of the binary signal, and at least to determine the phase relationship with the scanning clock for the binary signal of the same width. The same count value can be obtained in real time without being affected by the current flow, and accurate line width information can be obtained for subsequent processing such as pattern recognition, which is extremely effective.

[Brief explanation of the drawing]

FIG. 1 is a time chart when the phase relationship between the scanning clock and the binary signal is different. FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a time chart of the main parts. 1... Frequency divider, 2... Subtraction counter, 3... Memory circuit, 4... AND circuit, 5... Not circuit, 6
...and circuit, 7...and circuit.

Claims (1)

[Scope of utility model registration request] a frequency dividing circuit that divides an interpolation clock of a certain frequency by 1/n; an n-ary counter circuit that repeatedly counts using the interpolation clock only while there is no binary signal; a memory circuit that stores up to a constant value output of the n-ary counter circuit; an AND circuit that receives the Q output of the memory circuit and the scan clock that is the output of the frequency divider circuit; A line width detection circuit comprising an AND circuit which receives the Q output and presets an initial value to the counter circuit.