JPS62274675A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To specify the gate length not exceeding 0.5mum with excellent evenness and reproducibility by a method wherein a groove with normal mesa type section reaching the N type GaAs layer thereunder is formed on the second AlGaAs layer as the top layer to form a gate metal in the groove and then the second AlGaAs layer is removed. CONSTITUTION:A high purity GaAs layer 2, an N type AlGaAs layer 3, an N type GaAs layer 4 are epitaxially grown on a GaAs substrate to generate 2DEG5 and then the second AlGaAs layer 16 is formed on the N type GaAs layer 4. Next, a mesaetching part 17 is formed and both ends of the second AAlGaAs layer 16 are etched to form ohmic metallic electrodes 6, 7 as well as ohmic metallic diffused layers 8, 9 by heat treatment. Later, a photoresist 18 for masking groove with an opening is formed on the central part of the second AlGaAs layer 16 which is selectively etched to form a groove 19 with so-called normal mesa type section expanding upward.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention is directed to GaAl1I and Aj? The present invention relates to a method for manufacturing a field effect transistor (FET) using secondary electron gas (2DEO') formed at the interface with GaAs.

[Conventional technology]

Figures 4(a) to (e) are respectively conventional 2DEC)F'
This is a cross-sectional view showing an example of an ET. This 2 DEGFET can be roughly divided into two types: a planar structure [Fig. 4(a), (S)] and a groove structure [Fig. 4(c) to (e)]. be.

Figure 4 (a) KWhat is shown is not shown ()a
High purity GaA8ftj t on As substrate! l l
N-type AlciaAs layer! 31 + n-type GaAs layer (4
) are sequentially epitaxially grown to generate 2DEG (5), and an ohmic electrode (
6) and (7) to form an ohmic metal diffusion layer (
8).

(9) are formed respectively, and both ohmic electrodes +61
, (7) in which a gate electrode (11) is formed.

IE4 Figure (1)) The one shown in K is an improved version of
The structure shown in FIG. 4(e) has a p-type GaAs layer u1) provided below the gate electrode (10). However, the bottom of the groove (gong) remains within the n-type GaAs layer (4). The interface between the GaAs layer (4) and the n-type AlGaAs layer (3) or even the inside of the n-type AlGaAs layer (3) is shown in FIG. 4(e). Further, on the n-type AlGaAs layer (3) and the n-type GaAs layer (4), an AIGaAa layer α and an n-type GaAs layer
An As N layer is formed, and only the n-type GaAs layer has a groove-forming structure.

The structure of 2DEGFET can be roughly divided into 2 types as shown below.
Although there are several types, the planar structure shown in Figures 4(a) and (1) can be expected to improve the uniformity of transistor characteristics within the Wanow plane. Ohmic electrodes (
6) There is a manufacturing difficulty in that the intervals between (7) and (7) must be narrower than in the FETs having the grooved structure shown in FIGS. 4(0) to (e). Therefore, at present, Figure 4 (
Relatively many ohmic electrodes with the groove forming structures shown in 0) to (e) are manufactured.Next, we will explain the operation of the most common structure shown in Fig. 4(c). (6).

When a voltage is applied to (7), a current flows through the 2DEG (5), but at that time, when a voltage is applied to the gate electrode (11), the concentration of the 2DEG (5) under the gate changes, causing a transistor operation. Therefore, by adjusting the depth of the groove (2) forming the gate electric fence aO, the initial current value of the transistor can be adjusted and a 2DEGFET with desired characteristics can be manufactured.
[Problem to be solved by the invention] Conventionally, 2DEGFETs have generally been manufactured with a grooved structure compared to a planar type for the reasons mentioned above. In the structure shown in Figure 4 (C), the most important point is whether the line width is the narrowest (approximately 0.5 μm) even with the optical exposure method in order to shorten the gate length Lg. However, obtaining a line width smaller than this using an optical exposure method has many problems in terms of uniformity and reproducibility within the wafer surface.

In addition, in order to perform patterning with a line width smaller than this, electron beam exposure (EB) method, focused ion beam (FIB) method, etc.
Methods such as the method are currently being researched, but the current situation is that there are still many problems, such as the large scale of the equipment and the complexity.

A reduction in the gate length Lg results in a reduction in the gate-to-source capacitance Cgs and a reduction in the cutoff frequency f! rise in transconductance g. Shortening the gate length Lg is an important technical point for reducing noise and improving high frequency characteristics.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a 2DEGFET that can achieve a gate length of 0.5 μm or less even by a conventional optical exposure method.

[Means for solving problems]

In the method for manufacturing a 2DEGFET according to the present invention, an n
A second AlGaAs layer is further formed on the GaAs layer, and a second AJGaAe layer is formed using a reaction-controlled etchant to a depth that reaches the underlying n-type ()aAa layer. A trench is formed, then a gate metal is formed on the trench, and then the second AlGaAs layer is removed.

[Effect]

In this invention, the above procedure (therefore, 2D
When manufacturing an EGFET, a gate whose gate length is narrower than the line width patterned on the topmost second AIGaAa layer can be formed with good reproducibility, and a 2DEGFET with good uniformity can be easily obtained. be able to.

〔Example〕

FIG. 1 is a sectional view showing 2DE()PET manufactured by the method of one embodiment of the present invention. Hereinafter, the same reference numerals as those in the conventional example indicate equivalent parts, and the description thereof will be avoided from duplication.

In this example, a second AA'GaAsAlGa layer is formed on the n-type GaAs layer (4) on the n-type AIGILAe layer (3).
By selectively etching the As layer α0 and the second A#GaAs layer αfeK, a groove with a normal mesa-shaped cross section reaching the n-type GaAs layer (4) below is formed, and a gate metal electrode a is formed in the groove. ing.

The manufacturing method of this embodiment will be briefly described below with reference to FIG. High purity ()aAe on a GaAs substrate (not shown)
FJ t2) * n-type A7GaAs layer (3), n
The n-type GaAs layer (4) is epitaxially grown one after another to generate 2DEC) (5), and the n-type GaAs M (
4) Form a second AIGaAe layer σ on top of [Second
[Fig. 2 (a)] o Next, a mesa etching portion αη for isolation is formed [Fig. 2 (b)], and both ends of the second AlGaAs layer aQ are etched with hydrofluoric acid (HF) and hydrochloric acid (HR). ) selective etching with an etching solution to form micrometal electrodes [6) and (7) thereon, and then form a second photoresist (Fig. 2(e)).
Using this as a mask, for example, potassium iodide (K): iodine (2): water (H2O) = 226: 130
: 200 (weight ratio) by selectively etching the second Alc)aAs layer α with a reaction rate-limiting etchant such as
A groove α wound with a so-called mesa-shaped cross section that expands upward is formed by applying it to the groove [FIG. 2(f)].

This etchant is a Ga
For As, 3 × 10 μm/min, AII o, 3G
ao, with an etching rate of 1 μm/min for 7A8, GaAs and AIo, 30a. , 7As, the etching rate ratio is 1:30. Therefore, AlGa
As can be selectively etched relative to GaAs. Also, <o on C) aA8 substrate with (100) surface
The etched cross-sectional shape of the stripe groove in the i l direction is a so-called forward mesa shape having an angle of 54.7° with the surface. Therefore, since this etching solution is a selective etching solution and has a normal mesa-shaped cross section,
This method is suitable for mesa etching of the Aθ layer αQ. By utilizing the slope of the mesa-shaped groove cross section, even if the mask width at the surface is 0.5 μm, the Al()aAe layer σQ through the n-type GaAe layer (
4) The width of the groove bottom in contact with the groove bottom can be narrowed down to 0.5 μm or less, and the reproducibility of the width of the groove bottom is good. Furthermore, since the n-type GaAs layer (4) is used as a stopper for the etching groove, there is no need to adjust the current to control the depth of the groove when forming the groove, and advanced dry etching technology is used. Etching grooves with excellent reproducibility and uniformity within the wafer can be easily formed even without the use of etching grooves.

Next, the groove forming photoresist (g) is removed [Fig. 2 (ω)], and a gate electrode forming photoresist (1) with a large central opening is formed again [Fig. 2 (h)]. Using (1) as a mask, an upper Schottky gate metal α1 is formed on the mαα [FIG. 2(i)], and then the photoresist w for gate electrode formation is removed [FIG. 2(j)], and then , the second AlGaAs layer αQ is removed to complete the 2DEGFET of this example [Fig.
)].

As described above, in the 2DEGFET according to this embodiment method, the gate metal α■ in contact with the n-type GaAs layer (4) is
The (gate length) is determined by the film thickness of the second A/GaAs layer αQ on the top layer and the striped opening width of the trench-forming photoresist. 0 smaller than the striped opening width of
．． In the above example, in order to reduce ohmic resistance, the lower second AlGaAs layer α of ohmic metal +6), (7)
Although the case where G is removed is shown, if there is no need to particularly reduce the ohmic resistance, use the ohmic metal (6) as in another example shown in the cross-sectional view in FIG.

The second AIGaAe layer 0Q may be left under (7).

〔Effect of the invention〕

As described above, in the method for manufacturing a 2DEOFET according to the present invention, a groove with a normal mesa-shaped cross section is formed in the second Al()aAe layer as the uppermost layer so as to reach the n-type GaAs layer below. Form gate metal followed by second AgGa
Since the As layer was removed, the resist pattern for forming the grooves was formed with a thickness of 0.5 μm using a normal optical photolithography method.
Even when formed to a width of about m, the gate length determined by the width of the groove bottom has good uniformity and reproducibility of 0.5.

[Brief explanation of drawings]

FIG. 1 shows a 2
Figure 2 is a cross-sectional view showing the structure of DEC) PET; Figure 2 is a cross-sectional view showing the states at each step of the manufacturing method of this example;
The figure shows 2I) EGFE'I' manufactured by the method of this invention.
A sectional view showing the configuration of another example, FIG. 4 is a conventional 2DEG
FIG. 2 is a cross-sectional view showing a configuration example of an FET. In the figure, (2) is a high-purity GaAs layer, (3) is an n-type first AlGaAs layer, (4) is an n-type GaAe layer, (
5) is a two-dimensional electron gas, the back is a gate metal, (l is a second AlGaAs layer, and α is a forward mesa-shaped groove. In addition, the same reference numerals in the figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) Form a first n-type AlGaAs layer forming a heterojunction between the high-purity GaAs layer and form an n-type GaAs layer on the first n-type AlGaAs layer. Then, a second AlGaAs layer is formed on this n-type GaAs layer, and a groove is formed in this second AlGaAs layer, which has a mesa-shaped cross-sectional shape that expands upward and reaches the n-type GaAs layer. After forming a gate metal that makes a Schottky junction to the n-type GaAs layer through this groove, the second AlGaAs
A method for manufacturing a field effect transistor, comprising a step of removing an s-layer.