JPS6230295U - - Google Patents
Info
- Publication number
- JPS6230295U JPS6230295U JP12137885U JP12137885U JPS6230295U JP S6230295 U JPS6230295 U JP S6230295U JP 12137885 U JP12137885 U JP 12137885U JP 12137885 U JP12137885 U JP 12137885U JP S6230295 U JPS6230295 U JP S6230295U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- flushing
- information
- color
- representing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000011010 flushing procedure Methods 0.000 claims description 14
- 230000008094 contradictory effect Effects 0.000 claims 4
- 238000000034 method Methods 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000737 periodic effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Processing Of Color Television Signals (AREA)
Description
第１図は本考案の一実施例に係るフラツシング
回路の構成を示すブロツク図、第２図はブロツク
着色フレーム構成に対応するメモリ構成を示す概
念図、第３図ａ及びｂは第１図における信号のタ
イミング図、第４図は２相フラツシングを説明す
るための画面上の状態図である。
１１……ラツチ、１３……タイマ、１７，１９
，２３……アンドゲート、２５……マルチプレク
サ、３１……パターン面メモリ、Ｓ１……正相フ
ラツシング情報信号、Ｓ２……逆相フラツシング
情報信号、Ｓ３……ラツチコントロール信号、Ｓ
４……正相周期信号、Ｓ５……逆相同期信号、Ｓ
６……パターン情報信号、Ｓ７……背景色情報信
号、Ｓ８……前景色情報信号、Ｓ９……色情報信
号、Ｓ１０……フラツシング処理信号。
FIG. 1 is a block diagram showing the configuration of a flushing circuit according to an embodiment of the present invention, FIG. 2 is a conceptual diagram showing a memory configuration corresponding to a block colored frame configuration, and FIGS. 3 a and b are the same as those shown in FIG. The signal timing diagram, FIG. 4, is an on-screen state diagram for explaining two-phase flushing. 11...Latch, 13...Timer, 17, 19
, 23...AND gate, 25...Multiplexer, 31...Pattern surface memory, S1...Positive phase flushing information signal, S2 ...Negative phase flushing information signal, S3 ... Latch control signal, S
4 ... Positive phase periodic signal, S 5 ... Negative phase synchronous signal, S
6 ...pattern information signal, S7 ...background color information signal, S8 ...foreground color information signal, S9 ...color information signal, S10 ...flushing processing signal.
Claims (1)
ツシング情報信号を、フラツシングの対象指令情
報を表わす第３信号に基づいてラツチするラツチ
手段と、互いに相反する選択制御情報を表わす第
４及び第５の制御信号を発生する手段と、前記ラ
ツチ手段の出力信号と前記第４及び第５制御信号
とに基づいて第１フラツシシング処理の有無を表
わす第６信号を発生する手段と、前記第６信号と
第２フラツシング処理の有無を表わす第７信号と
に基づいて多重化選択信号を発生する手段と、前
記多重化選択信号に応じて互いに相反する色情報
を表わす２つの色情報信号を選択し、多重化され
た色信号を出力する手段とを有することを特徴と
するフラツシング回路。 ２ 前記互いに相反する色情報は、前景色及び背
景色を表わす情報であることを特徴とする実用新
案登録請求の範囲第１項に記載のフラツシング回
路。 ３ 前記フラツシング処理は、２相フラツシング
処理であることを特徴とする実用新案登録請求の
範囲第１項記載のフラツシング回路。 ４ 前記第４及び第５の制御信号は、互いに相反
する論理レベルを有する論理信号であることを特
徴とする実用新案登録請求の範囲第１項に記載の
フラツシング回路。[Claims for Utility Model Registration] 1. A latching means for latching first and second flushing information signals of mutually contradictory color information based on a third signal representing flashing target command information, and mutually contradictory selection control. means for generating fourth and fifth control signals representing information; and generating a sixth signal representing the presence or absence of the first flushing process based on the output signal of the latching means and the fourth and fifth control signals. means for generating a multiplex selection signal based on the sixth signal and a seventh signal representing the presence or absence of the second flushing process; 1. A flushing circuit comprising means for selecting a color information signal and outputting a multiplexed color signal. 2. The flushing circuit according to claim 1, wherein the mutually contradictory color information is information representing a foreground color and a background color. 3. The flushing circuit according to claim 1, wherein the flushing process is a two-phase flushing process. 4. The flushing circuit according to claim 1, wherein the fourth and fifth control signals are logic signals having mutually contradictory logic levels.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12137885U JPS6230295U (en) | 1985-08-07 | 1985-08-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12137885U JPS6230295U (en) | 1985-08-07 | 1985-08-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6230295U true JPS6230295U (en) | 1987-02-23 |
Family
ID=31010594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12137885U Pending JPS6230295U (en) | 1985-08-07 | 1985-08-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6230295U (en) |
-
1985
- 1985-08-07 JP JP12137885U patent/JPS6230295U/ja active Pending