JPS6230653B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a memory address control device for specifying a page address in a microcomputer.

Conventional configurations and their problems Improving instruction efficiency is one of the major issues in microcomputer design. Improving instruction efficiency refers to writing the execution of a certain control in a small-sized program. In other words, if the command system has less redundancy, it can be said to be an efficient command system. Of course, the efficiency of instructions varies greatly depending on the field of application, but the present invention describes a direct memory addressing method for microcomputers intended for relatively small-scale control applications.

Direct addressing is an addressing method in which the memory operation operand address is written in the instruction word. Conventionally, addressing in direct address mode involves either completely including the operand address in the instruction word, or valid only for a specific page (the memory block specified by the upper address part of memory is called a page). The idea was to create a command word. For example, in order to access a 64K word memory space, a 16-bit address is required, and even if the RAM area to be manipulated by a program is small, in the conventional example, addressing is specified using 16 bits when directly addressing. Ta. Furthermore, for example, a method has been used in which addresses 0 to 255 are designated as page 0, and a method is used in which direct addressing is performed using only 8 bits, with the restriction that only 0 pages are accessed. Although this is aimed at improving instruction efficiency by limiting the memory area, the field of application may be narrowed due to the limitation of the memory area.

Purpose of the Invention The present invention introduces two new direct addressing control flags to shorten the word length of instructions that specify arithmetic operands using direct addresses, and to address memory addresses that make it possible to access large address spaces. The purpose of this invention is to provide a control device.

Structure of the Invention In order to achieve the above object, the present invention has a register for register indirect specification consisting of an upper address register and a lower address register,
The lower address of the memory address is determined by the direct addressing part written in the instruction word, and the upper address of the memory address is set as a specific address, or
A first flag that selects and specifies whether the content of the upper address register is to be set, and for the same instruction word as above, the lower address of the memory address is set to the content of the lower address register, and the upper address of the memory address is set to the instruction. The device has a second flag for selecting a direct addressing section written in a word, and the first flag and the second flag can be controlled by a flag operation command.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below based on the drawings. FIG. 1 illustrates an example of the memory addressing mode of the present invention. There are H and L registers as memory address registers. H is an upper address register, and L is a lower address register. In the following description, it is assumed that the H and L registers are each 8-bit registers.

FIG. 1a shows the so-called register indirect addressing mode. That is, (H,L)
The contents of the memory specified by are the operands.

Figures 1b and 1c show addresses in direct addressing mode. The difference between b and c is that in the case of b, the upper address part is "0", and in the case of c, the upper address part is specified by the H register. Stated another way, b is the direct addressing mode in a particular page and c is the direct addressing mode in any page.

FIG. 1d shows an address mode in which the upper address part is designated by a direct address and the lower address part is designated by register L. How to use this mode will be explained later.

The key point of the present invention is that in the direct addressing mode, the same command words are used in FIG.
The present invention consists in introducing two direct address control flags DF _A and DF _B. For example, in the case of Figure 1 b, (DF _A , DF _B ) = (1, 0), and in the case of Figure 1 c,
(DF _A , DF _B )=(0, 0), and in the case of FIG. 1d, (DF _A , DF _B )=(0, 1).

FIG. 2 shows the instruction word structure of a load instruction L having register indirect and direct addressing modes according to the present invention. FIG. 2a shows the instruction word structure for the register indirect addressing mode, and FIG. 2b shows the instruction word structure for the direct addressing mode. The address mode in a load instruction is identified by the least significant bit (LSB) of the first word. In the direct addressing mode shown in FIG. 2b, addressing is controlled as shown in b, c, and d in FIG. 1 depending on the states of DF _A and DF _B.

FIG. 3 shows an example of the use of the direct address mode of FIG. 1d. Data closely related to the execution of arithmetic control is stored at the corresponding address of each page of memory, for example, address α on page 0, address α+256 on page 1, address α+512 on page 2, and address α+768 on page 3. It is often necessary to do so. At this time, α is pointed to by a register, but it is expected that the capacity of the processing program will be significantly reduced by directly pointing to the upper address part corresponding to the page. The reason why α, which is the lower address part, is specified by a register is that α
This is because they are often changed sequentially during program execution. For example, after completing the processing of the data stored at addresses 0, 256, 512, and 768, the register in the lower address part is incremented, and the data stored at addresses 1, 257, 513, and 769 is processed. Convenient for processing data.

That is, by adopting this addressing control system, three direct address modes can be processed using one instruction word. Here, it is possible to define instruction words for each of the above address modes without introducing an address control flag, but increasing the number of instruction words is not necessarily a good idea. This is because the word length of the instruction words of microcomputers is generally short, so assigning instruction words to instructions that are not used very frequently is disadvantageous in terms of the overall instruction system configuration. however,
Omitting all of these instructions, even if they are not used very often, could be a fatal flaw for a microcomputer.

FIG. 4 shows a configuration example of a memory address control method that implements the addressing methods described above. In FIG. 4, 1 is a first direct address control flag (DF _A ), and 2 is a second direct address control flag (DF _B ). Each DF _A , DF _B
1 and 2, not shown respectively.
The output signal from the instruction decoding section of the CPU is DF _A
Set signal line 11, _DFA reset signal line 12,
DF _B set signal line 13, DF _B reset signal line 14
Each signal line is connected to the set terminal and reset terminal of DF _A 1 and DF _B 2, respectively.
DF _A 1 and DF _B 2 are designated and controlled. 10 is a direct addressing control signal line, and in this circuit,
When in direct addressing mode, logical value “1”
A logical value "0" is applied in the register indirect designation mode. 16 is a direct address signal line to which a direct address is applied in the direct addressing mode.

3 is an upper address register H, and 4 is a lower address register L. AND gate 5 outputs "0" when the output of NAND gate 9 is "0",
When the output of NAND gate 9 is 1, the contents of register H3 are output. MUXA6 is a multiplexer, which outputs a direct address signal when the output of OR gate 8 is "0", and outputs the contents of register L4 when the output of OR gate 8 is "1". MUXB7 is a multiplexer, which outputs the output of the AND gate 5 when DF _B =0, and directly outputs an address signal when DF _B =1.

Next, the memory address generation operation by this circuit will be explained for each of cases a, b, c, and d in FIG.

In case a, direct address estimation control signal (signal on signal line 10) = 0 DF _A = 0 DF _B = 0 The contents of register H3 are output to the upper address 18 of the memory address through AND gate 5 and MUXB7. Furthermore, the contents of register L4 are stored in MUXA6 at lower address 17 of the memory address.
is output through.

For b Direct addressing control signal = 1 DF _A = 1
DF _B =0 The upper address 18 of the memory address is
The “0” signal generated by AND gate 5 is
Output through MUXB7. In addition, the direct address applied to the direct address signal line 16 is assigned to the lower address 17 of the memory address.
is output through.

In the case of c, direct addressing control signal = 1 DF _A = 0
DF _B =0 The upper address 18 of the memory address is
Through AND gate 5 and MUXB7, register H
The contents of 3 are output. Further, the lower address 17 of the memory address is directly connected to the address signal line 16.
The direct address applied to is output through MUXA6.

In the case of d, direct addressing control signal = 1 DF _A = 0
DF _B = 1 The upper address 18 of the memory address is
A direct address applied to the direct address signal line 16 is output via MUXB7. Also, at the lower address 17 of the memory address, there is a register L4.
The contents of are output through MUXA6.

As is clear from this explanation, the memory address control circuit shown in FIG. 4 enables the memory addressing described in FIG. 1.

Effects of the Invention As described above, according to the present invention, two direct addressing control flags that can be controlled by flag manipulation instructions are introduced, so it is possible to shorten the instruction word length during direct addressing, and at the same time Effective direct addressing as shown in d in Figure 1 becomes possible with a single instruction word, and as a result, a highly functional microcomputer with high instruction efficiency can be realized.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining an example of the memory addressing mode according to the present invention, FIG. 2 is a diagram for explaining an example of the instruction format of the register indirect and direct addressing modes of the present invention, and FIG. 3 is a diagram for explaining the example of the bank direct addressing mode. FIG. 4 is a memory address control circuit diagram showing an embodiment of the present invention. 1...Direct address control flag (DF _A ), 2
...Direct address control flag ( _DFB ), 3...
Upper address register, 4... Lower address register, 5... AND gate, 6... Multiplexer (MUXA), 7... Multiplexer (MUXB).

Claims (1)

[Claims] 1 It has a register for indirect register specification consisting of an upper address register and a lower address register, and determines the lower address of a memory address by the direct address specification section written in the instruction word, and the upper address of the memory address. A first flag that selects and specifies whether to use a specific address or the contents of the upper address register, and a memory address that sets the lower address of the memory address to the contents of the lower address register for the same instruction word as above. The first flag and the second flag are controllable by a flag manipulation command. memory address control device.