JPS6230656B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method of retrying each retry unit once when a failure occurs in a computer.

(2) Conventional technology and problems When a failure occurs in a computer, a record of the failure status is kept for maintenance, etc., and then the status is returned to the status before the failure and the process where the failure occurred is retried (retry).
This is very effective in cases of intermittent disorders. Therefore, in a computer, when a failure occurs in each microinstruction unit, machine instruction unit, or each instruction group, the changed data is restored using the saved data and the process is retried. At this time, if the restored data is different from the original data due to a design error, the retry will corrupt the data, and retrying will only make the situation worse. For this reason, in computers with a retry function, it is very important to check whether the function operates correctly, and for this purpose, a method of forcibly causing an error state has been used in the past. However, this conventional method has the disadvantage that there are restrictions on the location and timing of error occurrence, and that it is not possible to check the validity of retries in all cases of processing flowing in a complex sequence.

(3) Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks and provide a method that guarantees the validity of all retries by always performing retries in all processing within a computer. .

(4) Structure of the Invention The object is to provide a retry mode setting means for checking the retry function and a retry mode setting means in a computer equipped with means for retrying from a preset check point when a failure occurs. This is achieved by a retry control method characterized by providing means for executing ranking retry in preset retry units based on a set function check mode.

(5) Embodiments of the Invention The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 11 is a register group, 12 is a memory, 13 is an instruction control circuit, 14 is a retry control circuit, 15 is a retry mode control circuit, 16 is an arithmetic circuit, 17 is a save circuit, 18 is a retry mode, and 19 is a retry timing. , 110 is
RTRYINH, 111 is a retry processing routine activation signal, P is an error occurrence signal, Q is a clock stop, and R is a SCANOUT.

FIG. 2 is a diagram showing details of a save circuit, etc., showing an embodiment of the present invention.

In the figure, 21 is REGSAVE, 22 is
ICSAVE, 23 is an IC, and A to D are registers.

FIG. 3 is a diagram showing details of a retry control circuit according to an embodiment of the present invention.

In the figure, 31 is an error processing circuit, and 32 is an error processing circuit.
SCANOUT circuit 33 is a retry processing circuit.

FIG. 4 is a diagram showing details of a retry mode control circuit according to an embodiment of the present invention.

In the figure, 41 is a retry start signal, 42 is a machine instruction execution end signal, and 43 is a timing.

Now, in the present invention, the retry mode 18 is set to 1 in the retry mode control 15 and the retry timing 19 is set to 1.
At the timing specified by , if RTRYINH110 is 0, a retry processing routine activation signal 111 is generated, and this signal activates the retry control circuit 14, and the retry control circuit stops the clock,
It resets the instruction control circuit 13, restores the source data from the save circuit, and rereads and processes the machine instruction to be retried. If the retry timing 19 indicates the timing of the first step to the last step of each machine instruction, a retry processing routine activation signal 111 is generated for each machine instruction, and each machine instruction is processed while being repeatedly retried. (In this case, the difference from the processing when an error occurs is that SCANOUTR is not performed after the clock is stopped. Since SCANOUT takes time, each machine instruction is retried.
Executing SCANOUTR takes too much time and is not practical. ) The role of the RETRYINH 110 signal or latch is to prevent the same machine instruction from being retried repeatedly when retrying a machine instruction. When the processing routine start signal 111 is generated at the timing of , and the machine instruction 1 (retry unit) is retried, the machine instruction 1 and machine instruction 2 (retry unit) are retried again at the timing specified by the retry timing 19 of the machine instruction 2 (retry unit). This prevents the processing routine activation signal 111 from being generated.

To check for retry, if you take a checkpoint at a certain point in the flow of processing instead of causing a pseudo failure, the process will be forcibly interrupted before taking the checkpoint at the next point, and the saved data will be lost. If you return to
Furthermore, the same process is repeated, that is, the retry unit is always retried once.

(6) Effects of the Invention As explained above, according to the present invention, all processing is always retried, and the validity of the retry can be guaranteed in all cases.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a diagram showing details of a save circuit, etc., showing an embodiment of the present invention. FIG. 3 is a diagram showing details of a retry control circuit according to an embodiment of the present invention. FIG. 4 is a diagram showing details of a retry mode control circuit according to an embodiment of the present invention. 11 is a register group, 12 is a memory, 13 is an instruction control circuit, 14 is a retry control circuit, 15 is a retry mode control circuit, 16 is an arithmetic circuit, 17 is a save circuit, 18 is a retry mode, 19 is a retry timing, and 110 is a RTRYINH, 111 is the retry processing routine start signal, P is the error occurrence signal, Q is the clock stop, and R is the SCANOUT.

Claims (1)

[Claims] 1. In a computer equipped with a means for executing a retry (retry) from a preset check point when a failure occurs, a retry mode setting means for checking the retry function and a function check mode set by the retry mode setting means. 1. A retry control method comprising means for sequentially executing retries in preset retry units based on the above information.