JPS6231265A - Modified huffman decoding system - Google Patents

Abstract

PURPOSE:To reduce states of decision by deciding two bits of a picture signal to be decoded. CONSTITUTION:During starting of a processing, '00' is inputted to a state number of an address input of a ROM12, a white and black indicating signal B/W is inputted to an address input by a decoding of a white run-length or a decoding of a black run-length. In this state, a controller 13 supplies a shift clock to a shift register 14 twice, as a result, the first bit and the second bit of a code to be decoded are inputted to an address of the ROM12. When a value of the two bits are any of (0,0) (0,1) (1,0) (1,1), an output corresponding to a state conversion diagram. The controller 13 inputs a shift clock to a shift register and every time when the two bits of an encoding signal are inputted, the state of the ROM12 is moved from the '00' state to the right. When a decoding processing is completed by the last one bit, the controller 13 outputs the next shift clock only once by receiving a decoding remaining one bit deciding signal from the ROM12 and the decoding is completed in the next state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a decoding method for decoding a facsimile signal from a modified Huffman encoded facsimile signal.

[Conventional technology]

7 axis) Modified human code (MH code) is used as a coding method for suppressing redundancy in CCI signals.
'l' T has been recommended and is widely used in general.
As shown in the figure. This is an application of the decoding circuit for the No-Fuman code (Patent Application No. 525158 of 1972).

The controller 23 sets the latch circuit 21 at the start of processing, and sends a black-and-white instruction signal B to the read-on memory (ROM) 22 to indicate whether decoding of the white run length or black run length of the MH code is to be decoded from now on. /W indicates.

The ROM 22 undergoes different state transitions for the white run-length decoding and black run-length signals, respectively. This figure 4 shows a state transition diagram during decoding of black run length, and shows the state transition diagram when the number of pixels in one line is 2560 pixels.
A part of the state transition of OM22 is shown. In FIG. 4, the values on the line indicate encoded data input to the ROM 22, and the numbers above the circle indicate the address input of the ROM 22 and the output of the previous ROM.

In FIG. 4, at the start of processing, "00" is input to the state number of the address input of R, 0M22, and whether the white run length is decoded or the black run length is decoded, the black and white instruction signal B/ W is input to the address input. In this state, the controller 23 supplies a shift clock to the shift register 24, and as a result, the first bit of the code to be decoded is input to the address of R, OM 22. R.O.
M22 is R, 0M2 depending on whether the signal is 0#, 11" or K.
2 is output as "01" or 102#. In this way, the controller 23 inputs the shift clock to the shift register 24, and each time the code signal to be decoded is input by one bit, the state of the ROM 22 changes from the @00# state to the right in FIG. When the decoding is completed, the ROM 22 outputs the decoded data and an end determination signal to the controller 23, and the decoding of one code signal to be decoded is completed.

[Problem that the invention seeks to solve]

The conventional decoding circuit described above changes the state of the ROM 22 for each bit of the input image signal.
It was necessary to set many states of 2.

[Failure to solve the problem]

The sodi7aidha7man decoding method of the present invention is
A shift register that performs parallel-to-serial conversion of a facsimile image signal encoded by Id-Huffman, and a 2-bit leading serial output of the shift register % Is the facsimile image signal decoding based on the white run length or black run length? A read-only device that outputs a pre-stored n-bit second state number-indicating signal using a 1-bit black-and-white instruction signal and an n-bit (n>0) first state number-indicating signal as input addresses. a latch circuit that latches the output of the read-only memory and outputs it as the first state number instruction signal; and a latch circuit that latches the output of the read-only memory and outputs it as the first state number instruction signal; The present invention is characterized by comprising a controller that shifts the register by 2 bits, and shifts the shift register by 1 bit when the decoding remaining bit determination signal indicates that there is 1 bit remaining.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the invention. 11 is a latch circuit;
12 is a ROM, 13 is a controller, and 14 is a shift register. At the start of processing, the controller 13 resets the two-way circuit 11 and instructs the ROM 12 whether the white run length or the black run length of the MH code is to be decoded from now on using a monochrome instruction signal B/W. ROM1
2 has different state transitions for the decoding of the white run length and the decoding of the black run length. FIG. 2 shows the state transition during black run-length decoding, and shows a part of the state transition when the number of pixels in one line is 2560 pixels. Second
In the figure, the values on the line indicate encoded data input to the ROM 12, and the numbers above the circle mark indicate the input of the address of the ROM 12 as well as the output of the ROM 12 one previous time in the state transition. The 1-digit number below the circle is used to determine whether only 1 bit or 2 bits of data are required to be decoded by the end of decoding.

In Fig. 2, at the start of processing, @oo'' is input to the state number of the address input of the ROM 12, and the black and white instruction signal B/W is input to the address, depending on whether it is decoding of white thin length or black run length. In this state, the controller 13 supplies the shift clock to the shift register 14 twice, and as a result, the first and second bits of the code to be decoded are input to the address of the ROM 12.

The value of those two bits is (0,0)(0,1)(1,0)(
1, 1) outputs an output according to the state transition diagram. In this way, the controller 13 inputs the shift clock to the shift register, and each time 2 bits of the encoded signal are input, the state of the ROM 12 changes from the '00# state to the right, and the encoded signal to be decoded changes from the '00# state to the right. When it is an odd number of bits and the decoding process ends at the last bit, the ROM 12 outputs a decoding remaining bit determination signal (11") indicating that there is 1 bit remaining for decoding, and the signal The controller 13 that has received the signal outputs the next shift clock only once, completes the decoding in the next state, and outputs an end signal.

[Effect of idea]

As explained above, the present invention can reduce the number of determination states by determining the image signal to be decoded 2 bits at a time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a block diagram of the conventional example, and FIG. 4 is a state transition diagram of the ROM in FIG. 3. 11...--Latch circuit, 12... Read-only memory, 13... Control circuit, 14...
...Shift register, 21...Latch circuit,
22... Read only memo 1c 23...
...Control circuit, 24...Shift register. No. F

Claims (1)

[Claims] A shift register that performs parallel-to-serial conversion of a modified Huffman encoded facsimile image signal, a 2-bit leading serial output of the shift register, and a determination as to whether the facsimile image signal is decoded using a white run length or a black run length. A read-only memory that outputs a pre-stored n-bit second state number instruction signal using a 1-bit black and white instruction signal and an n-bit (n>0) first state number instruction signal as input addresses. a latch circuit that latches the output of the read-only memory and outputs it as the first state number instruction signal; and a shift register when the decoding remaining bit determination signal from the read-only memory indicates that there are 2 bits remaining. a controller for shifting the shift register by 2 bits, and shifting the shift register by 1 bit when the decoding remaining bit determination signal indicates that there is 1 bit remaining.