JPS623132U - - Google Patents
Info
- Publication number
- JPS623132U JPS623132U JP9317885U JP9317885U JPS623132U JP S623132 U JPS623132 U JP S623132U JP 9317885 U JP9317885 U JP 9317885U JP 9317885 U JP9317885 U JP 9317885U JP S623132 U JPS623132 U JP S623132U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- stereo
- transistor
- demodulation circuit
- muting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002131 composite material Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Noise Elimination (AREA)
Description
第１図は本考案のチユーナにおける利得調整回
路の回路図、第２図はＦＭステレオ放送とテレビ
ジヨンの音声多重放送が受信可能な受信機のブロ
ツク系統図である。
３……ＦＭステレオ復調回路、４，６……ミユ
ーテイング回路、５……ＴＶ多重復調回路、８…
…制御電圧発生回路、Ｑ１，Ｑ２……トランジス
タ、Ｒ２，Ｒ３，Ｒ４……抵抗。
FIG. 1 is a circuit diagram of a gain adjustment circuit in a tuner according to the present invention, and FIG. 2 is a block system diagram of a receiver capable of receiving FM stereo broadcasts and television audio multiplex broadcasts. 3... FM stereo demodulation circuit, 4, 6... Muting circuit, 5... TV multiplex demodulation circuit, 8...
...Control voltage generation circuit, Q1 , Q2 ...Transistor, R2 , R3 , R4 ...Resistor.
Claims (1)
重復調回路と、前記ＦＭステレオ復調回路と前記
テレビジヨン音声多重復調回路にステレオ複合信
号をおのおの供給するための第１のトランジスタ
と、テレビジヨン音声多重放送受信時に前記ＦＭ
ステレオ復調回路の出力信号をミユーテイングす
るための第１のミユーテイング回路と、ＦＭステ
レオ放送受信時に前記テレビジヨン音声多重復調
回路の出力信号をミユーテイングするための第２
のミユーテイング回路と、前記第１および第２の
ミユーテイング回路とスイツチング用の第２のト
ランジスタを制御するための制御電圧発生回路と
を備え、ＦＭステレオ放送受信時に前記第２のミ
ユーテイング回路が動作すると共に前記第２のト
ランジスタのコレクタ―エミツタ間が導通状態と
なり、この導通状態により、前記第１のトランジ
スタがエミツタ接地型増幅回路として動作するよ
うにしたことを特徴とするチユーナにおける利得
調整回路。 an FM stereo demodulation circuit, a television audio multiplex demodulation circuit, a first transistor for supplying a stereo composite signal to the FM stereo demodulation circuit and the television audio multiplex demodulation circuit, respectively; Said FM
a first muting circuit for mutating the output signal of the stereo demodulation circuit; and a second muting circuit for mutating the output signal of the television audio multiplexing demodulation circuit when receiving FM stereo broadcasting.
and a control voltage generation circuit for controlling the first and second muting circuits and a second transistor for switching, wherein the second muting circuit operates when receiving an FM stereo broadcast. A gain adjustment circuit for a tuner, characterized in that the collector-emitter of the second transistor is in a conductive state, and this conductive state causes the first transistor to operate as a common emitter type amplifier circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9317885U JPS623132U (en) | 1985-06-20 | 1985-06-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9317885U JPS623132U (en) | 1985-06-20 | 1985-06-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS623132U true JPS623132U (en) | 1987-01-09 |
Family
ID=30650622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9317885U Pending JPS623132U (en) | 1985-06-20 | 1985-06-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS623132U (en) |
-
1985
- 1985-06-20 JP JP9317885U patent/JPS623132U/ja active Pending
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