JPS6231399B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse conversion device that inputs multiphase pulses emitted from a wattmeter, for example, in proportion to usage, converts them into pulses of any shape or number, and outputs the pulses. It is.

Conventionally, this type of pulse converter drives a pulse motor using pulses sent from a wattmeter.
The rotational force was transmitted through a gear train with a ratio to set the pulse conversion ratio to a transmitter that generated the pulse of the type to be output, and the pulse was output. However, since the pulse converter is composed of mechanical parts such as a pulse motor and a gear train, its lifespan is short, the mechanism is complicated, and its size cannot be made small. Furthermore, since a gear train is used, there are problems such as the inability to respond to fast-cycle pulses, or when the input pulse frequency or phase sequence changes suddenly. Furthermore, the pulse conversion ratio is set by the gear ratio of the gear train, so if you want to set it to an arbitrary conversion ratio, it is necessary to prepare gears with many combinations of gear ratios, and it is necessary to assemble them. required a large amount of time.

This invention was made in view of the above-mentioned drawbacks, and uses an electronic circuit to achieve good responsiveness.
The purpose is to provide a low-cost, highly reliable pulse converter that can set any conversion ratio.

An embodiment of this invention will be described below.

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention. Reference numeral 1 denotes a phase order discriminating circuit. Three-phase pulses are input to terminals R ₁ to R ₃ , and the phase order of the pulses is determined as shown in FIG. 2. When is in positive phase, a pulse is output to terminal Q ₁ , and when it is in negative phase, it is output to terminal Q ₂ . Reference numeral 2 denotes an addition/subtraction counter (hereinafter referred to as a U/D counter), which adds and counts when a pulse is input to terminal A, and subtracts when it inputs to terminal B. The contents of the counter are at the terminal
Output to Q ₀ and Q ₁ . That is, when the content of the counter is 0, Q ₀ becomes a logic 1 (hereinafter referred to as 1) and Q ₁ becomes a logic 0 (hereinafter referred to as 0), and when a pulse is input to terminal A, an addition count is made and the counter becomes 0.
As above, Q ₀ becomes 0 and Q ₁ becomes 1. On the other hand, when a pulse is input to B, the count is subtracted, the counter becomes 0 or less, and both Q ₀ and Q ₁ become 0. 3 is 3
The phase pulse output circuit is configured to apply a clock to terminal T and output three-phase pulses of positive phase when terminal E is 1 and negative phase when terminal E is 0 to terminals C ₁ to C ₃ . 4
is a counter for setting the pulse conversion ratio, and when the count ends, a narrow differential pulse is output from the terminal Q. This pulse is used by the phase order discriminator circuit 1.
This is done so that it does not overlap with the pulses output from Q ₁ and Q ₂ . 5 and 6 are D flip-flops (hereinafter referred to as FF), and when the output Q of FF 5 is 1, a pulse φ is sent to a three-phase output circuit 3 and a counter 4. FF6 is for determining the phase order of three-phase output pulses, and _Q1 of U/D counter 2 is set to FF5.
It is latched by Q of . 7 and 8 are OR gates 9 to 12 are AND gates, and 13 is an inverter that inverts the input and at the same time outputs the input pulse with a slight delay. The degree of delay is slightly longer than the pulse width output from Q of the counter 4. FIG. 3 is a timing chart for explaining the operation of the configuration shown in FIG.

The operation will be explained below.

Figure 2 is a timing chart for explaining the operation of the phase order discrimination circuit 1. During the period _T1 , the watt-hour meter transmits positive-phase pulses in the order of _R1 → _R2 → _R3 in a manner that partially wraps them. are doing. During T ₂ , the pulses of the watt-hour meter are in reverse phase, and the order is R ₃ → R ₂ → R ₁ . Then, during the positive phase period _T1 , for example, the differential pulse of the leading edge of the _R1 pulse and the logical AND of the _R3 pulse, and the logical AND of the differential pulse of the leading edge of the _R2 pulse and the _R1 pulse are taken. If the outputs of are combined using logical OR, a pulse like Q ₁ shown in the second diagram will be obtained.
During the period T ₂ of the opposite phase, for example, the differential pulse of the leading edge of the R ₁ pulse is ANDed with the R ₂ pulse, and the differential pulse of the leading edge of the R ₃ pulse is ANDed with the R ₁ pulse. If they are combined, a pulse like Q ₂ shown in the second diagram will be obtained.

In the embodiment shown in FIG. 1, the pulse conversion ratio is set such that 1 pulse of 3-phase input becomes 3 pulses of 3-phase output, and the 3-phase output circuit 3 outputs 1 pulse of 3-phase for 2 pulses of the clock, for example. Therefore, when the counter 4 counts 6 pulses, a pulse is sent from Q.

FIG. 3 is a timing chart for explaining the operation of the circuit shown in FIG. 1, and it is assumed that the U/D counter 2, counter 4, and FF 5 are reset before time _t1 . Now, at time t ₁ , phase order discriminator circuit 2
From Q ₁ via OR gate 7, U/D counter 2
When a pulse is input to addition input A of
, Q ₀ becomes 0 and Q ₁ becomes 1. Since Q ₀ of U/D counter 2 is connected to T of FF5 via inverter 13, when Q ₀ changes from 1 to 0, Q of FF5 is changed to 1 with a slight delay. FF5's Q is 1
When it becomes, FF6 opens at the same time as AND gate 9 is opened.
₁ of Q1 of U/D counter 2 is latched.
When Q of FF6 becomes 1, it becomes positive phase mode and 3
The AND gate 11 is opened in order to output a positive phase pulse from the phase output circuit 3, and to guide the pulse sent out from the Q of the counter 4 at a later time point _t2 to the subtraction input B of the U/D counter 2. , closes the AND gate 12. Since AND gate 9 is open, clock φ is sent to counter 4 and three-phase output circuit 3. At time _t2 , counter 4 changes clock φ to 6
After counting the pulses, send the pulses from Q. This pulse is input to the subtraction input B of the U/D counter 2 via the AND gate 11 and the OR gate 8. The contents of U/D counter 2 are calculated by subtracting 1 from the value added at t ₁ above, and it becomes 0, so Q ₀ is 1 and Q ₁ is 0.
become. The pulses sent from Q0 of ₁ and Q of count 4 reset FF5 through AND gate 10, and close AND gate 9 to complete the operation.

If one more pulse is input to the addition input A of the U/D counter 2 between times t ₁ and t ₂ , the contents of the U/D counter 2 are added from 1 to 2. During this time, the operation after _t1 is continued. Next, when a pulse is sent from Q of counter 4 after counting 6 pulses in the same way as t ₂ , U/D counter 2 is subtracted and the content changes from 2 to 1, but since Q ₀ is 0, FF5
is not reset, and the AND gate 9 remains open and continues the same operation as after _t1 . Counter 4 again sends out a pulse from Q after counting 6 pulses, and changes U/D counter 2 from 1 to 0. Here, Q ₀ becomes 1 for the first time, so the same as in the case of t ₂
FF5 is reset and the operation ends. During this time, the counter 4 is counting 12 pulses and outputting 6 three-phase pulses in response to 2 pulses input to the U/D counter.

At time t ₃ , _the phase order discrimination circuit 2
A pulse is input from Q ₂ to the subtraction input B of the U/D counter 2 via the OR gate 8. U/D counter 2 counts down, and the contents of the counter are -
1, and both Q ₀ and Q ₁ become 0. When Q ₀ of the U/D counter changes from 1 to 0, the same as at t ₁
Q of FF5 is set to 1, AND gate 9 is opened, and at the same time, ₀ of Q1 of U/D counter 2 is latched to FF6, and Q is set to 0. When FF6's Q is set to 0,
The three-phase output circuit 3 is in reverse phase mode until time _t4 .
At the same time as outputting the phase pulse, AND gate 11
, and open AND gate 12. When the AND gate 9 opens and the counter 4 finishes counting six pulses of the clock φ, a pulse is sent from Q at time _t4 . This pulse is input to the addition input A of the U/D counter 2 via the AND gate 12 and the OR gate 7, and is added to -1, the value subtracted at _t3 , to make the counter content 0, and _Q0 becomes 1. Similarly to t ₂ , 1 of Q ₀ of U/D counter 2 and counter 4
The FF 5 is reset by the pulse sent from the Q of the FF 5, the AND gate 9 is closed, and the operation is completed.

Next, at time _t5 , addition input A of U/D counter 2
One pulse is input to , and the same operation as at t ₁ begins. When a pulse is input to subtraction input B at time _t6 , when a pulse has not yet been sent from Q of counter 4, the content of U/D counter 2 changes from 1 to 0.
Q ₀ becomes 1 and Q ₁ becomes 0. However, at this point, _Q0 of the U/D counter 2 is 1, but since no pulse is sent from the output Q of the counter 4, the FF 5 is not reset and continues to operate in the normal phase mode. When a pulse is sent out from Q of counter 4 at time t ₇ , U/D counter 2 has already
Since the contents of Q0 have become 0 and _Q0 has become 1, FF5 is immediately reset and at the same time,
The Q pulse of the counter 4 passes through the AND gate 11 and the OR gate 8 to subtract the value of the U/D counter 2, making the contents of the counter -1, and both Q ₀ and Q ₁ become 0. Since Q ₀ is connected to T of FF5 via the inverter 13 that performs the delay and inversion operation described above, when the pulse of Q of counter 4 disappears,
FF5 is set to 1 again, AND gate 9 is opened, and FF6 is set to reverse mode at the same time, and thereafter the same operation as at _t3 is performed, and the operation is ended at time _t8 . point in time
At t ₇ , inverter 13 changes Q ₀ of U/D counter 2.
After becomes from 1 to 0 and the pulse sent from Q of counter 4 disappears, set FF5 to 1.
Since the FF 6 is in the reverse mode, the pulse sent out from the counter 4 at t ₇ will not be input to the addition input A of the U/D counter 2 again.

In the above explanation, for example, after t ₃ , the Q of counter 4 is
If the second pulse is applied to the subtraction input B of the U/D counter 2 before the pulse is sent from
Alternatively, the case where two or more pulses are input to the U/D counter 2 before being sent out from the Q of the counter 4 is not explained, but if the number of bits of the U/D counter 2 is appropriately selected, , the output can be obtained in proportion to the input, similar to the operation described above. Also, for example, the addition input A from the phase order discrimination circuit 1
When 3 pulses are input to , and immediately 2 pulses are input again from the phase order discrimination circuit 1 to the subtraction input B, the above pulses are canceled out in the U/D counter 2 and the content of the counter becomes 1, which corresponds to one input pulse. When only one pulse is output from the counter 4, the operation ends.

In the above embodiment, the pulses emitted from the watt-hour meter and the pulses output from this pulse converter were explained as three phases, but the pulses are limited to only three phases as long as the forward directionality of the pulses can be determined. It's not something you can do. In addition, although the input pulse is separated into forward and reverse, if the normal phase or reverse phase mode is predetermined, which one of FF6, AND gate 11 or 12, or OR gate 7 or 8, which determines the forward or reverse mode, is used. Alternatively, the output _Q1 of the U/D counter 2 may be omitted.

As described above, according to the present invention, a simple circuit is used and mechanical parts are omitted, resulting in high reliability and long life, and a gear train for setting the pulse conversion ratio. Since no skill is required for assembly, the assembly time can be shortened, and the pulse conversion ratio can be set arbitrarily by simply determining the count value of counter 4, and the U/D counter 2 can be set to an appropriate number of bits. By setting the clock φ to an appropriate frequency, even if short-cycle pulses are input to the terminals R ₁ to _{R 3} of the phase order discrimination circuit 1, it is possible to drive a measuring instrument with a low tracking speed, which has great practical effects. A pulse converter can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the phase order discrimination circuit in FIG. 1, and FIG. 3 is a diagram showing the operation of the circuit in FIG. 1. This is a timing chart for explanation. 1...Phase order discrimination circuit, 2...U/D counter, 3...
Phase output circuit, 4... Counter, 5, 6... D flip-flop, 7, 8... OR gate, 9 to 12... AND gate, 13... Inverter.

Claims (1)

[Claims] 1. A phase order determination circuit that receives an input pulse whose phase order can be determined and determines the phase order from the input pulse, a temporary memory circuit that temporarily stores that there is an output of the phase order determination circuit, and an output for the input pulse. A pulse ratio setting circuit that sets a ratio of pulses, a phase sequence mode determining circuit that determines a phase sequence mode of output pulses according to a phase sequence of input pulses based on the outputs of the temporary storage circuit and the pulse ratio setting circuit, and this phase sequence mode determining circuit. 1. A pulse converter comprising a pulse output circuit that outputs multiphase pulses having a required phase order and pulse ratio according to the output of the pulse converter.