JPS6231460A - Memory protecting circuit - Google Patents

Abstract

PURPOSE:To secure data on a memory in a transient state where a power supply is switched by setting two levels of monitor detecting voltage of a primary power supply in order to use them for switching of the power supply of a CMOS memory and for each control for chip selection. CONSTITUTION:The output of a voltage monitor circuit 30 is changed to H from L at a time point when the voltage of a primary power supply 1 is reduced down to 4.5V from 5V. Thus a memory protecting signal is changed to L from H and a CMOS memory 3 is put under a writing inhibition state. When the power supply 1 is reduced more down to 4.0V, the output of a voltage monitor circuit 20 is changed to H from L. Then a power supply switching circuit 10 switches the power supply 1 to an auxiliary power supply 2 for supply of power to the memory 3 by the signal of the circuit 20. Thus the power of 3.6V is supplied to the memory 3. When the voltage of the power supply 1 rises up again, the power supply is switched and the writing inhibition mode of the memory 3 is released.

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a memory protection circuit, and in particular to a memory protection circuit that protects a CMOS memory in which a part of microprocessor programs and processing data is stored from power abnormalities (power outages, instantaneous interruptions, etc.). Regarding circuits.

■】J【■ Traditionally, C in systems using microprocessors
The MOS memorive O protect circuit detects that the voltage of the main power supply has dropped and switches to the auxiliary power supply, and at the same time
A method is used to prevent data destruction by controlling the chip select (C3) terminal of the S memory to inhibit data writing.

FIG. 4 is a block diagram showing an example of such a conventional memory processor 1 to circuit, in which 1 is a main power supply, 2 is an auxiliary power supply, 3
is CMOS memory, 4.5 is power input, 6 is power output,
7 is a memory protect signal output, 10 is a power supply switching circuit,
20 is a voltage monitoring circuit, 40 is a reference voltage source, and 50 is a memory protect signal generating circuit.

Now, assuming that the main power supply voltage is 5V, the auxiliary power supply voltage is 3°6, and the voltage drop detection voltage of the voltage monitoring circuit 20 is 4V, the operation of the circuit shown in FIG. 4 is explained with the waveform diagram shown in FIG. Ru. In other words, if the main power supply voltage drops to 4.4
．． When the voltage falls below 0V, the output of the voltage monitoring circuit 20 changes from low level to high level. As a result, the power supply switching circuit 10 switches the power supply to the CMOS memory 3 from the main power supply to the auxiliary power supply.Furthermore, since the memory program signal changes from high level to low level, the CMOS memory chip select (C3 ') terminal becomes low level, and data writing to CMOS memory 3 is prohibited.After that, when the main power supply voltage is restored to 4.0V or higher, the power supply to the CMOS memory is switched to the main power supply, and the CMOS memory is Data write protection is also lifted.

However, when the circuit shown in FIG. 4 is used, there is a risk that data may be accidentally destroyed in a transient state of power supply switching. Furthermore, if there are a large number of CMOS memories and a large amount of current is consumed during normal operation, there is a disadvantage that noise is generated when switching the power supply, which causes data corruption in the CMOS memory.

OBJECT OF THE INVENTION It is an object of the present invention to
It is an object of the present invention to provide a memory protection circuit that can reliably protect data in an O'S memory.

Structure of the Invention A memory protect circuit according to the present invention is a memory protect circuit that protects memory data in the event of an abnormality in the main power supply, and includes a power supply switching means that switches to an auxiliary power supply when the absolute value of the voltage of the main power supply is below a predetermined threshold. , write inhibiting means having a second threshold value larger than the predetermined threshold value and inhibiting data writing when the absolute value of the voltage of the main power source is equal to or less than the second threshold value. It is characterized by

Example Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a CMOS memory protect circuit according to the present invention. In FIG. 1, parts common to those in FIG. 4 showing the conventional example described above are given the same symbols and names, and the details thereof will be omitted.

Now, the main power supply 1 is 5V, the auxiliary power supply 2 is 3.6V, the voltage drop detection voltage (threshold) of the voltage monitoring circuit 20 is 4.0V, the voltage drop detection voltage RJ value of the voltage monitoring circuit 3o)+, 14.
5V, CMOS memo 'J3 is chip select (CS)
It is assumed that when the terminal is at a low level, the memory is protected, that is, write is prohibited.

FIG. 3 shows the operating waveforms of this embodiment.

First, the voltage of the main power supply 1 drops from 5V, and when it reaches 4.5V, the output of the voltage monitoring circuit 30 changes from low level to high level, and the memory protect signal changes from high level to low level. The CM OS memory becomes write-protected. Next, the main power supply 1 decreases further and 4. O
When the voltage reaches V, the output of the voltage monitoring circuit 20 changes from low level to high level, and this signal causes the power supply switching circuit 10 to change from low level to high level.
switches the power supply to the CMOS memory from the main power supply to the auxiliary power supply. In other words, while the main power supply 1 is below 4.0V, the CMO
The S memory is supplied with 3.6μ power from the auxiliary power supply.

When the main power supply 1 becomes W voltage again, the power supply is first switched in the reverse order as described above, and then the write protection of the CMOS memory is released.

FIG. 2 is a circuit diagram showing one embodiment of the present invention shown in FIG. 1. The power supply switching circuit 10 includes a resistor 11°12.14,
It is composed of transistors 13, 15, and 16, and when transistor 16 is turned on and off by the output signal of voltage monitoring circuit 20, transistors 15 and 13 are turned off and on, respectively. The voltage monitoring circuits 20 and 30 include operational amplifiers 23.
33 and voltage dividing resistors 2i, 22, 31, and 32, the main power supply voltage is divided by the voltage dividing resistors and compared with the voltage of the reference voltage source 40. A reference voltage source 40 includes a resistor 41 and a Zener diode 4, both of which are connected to the auxiliary power source 2.
2, which always generates a constant reference voltage. The memory protect signal generating circuit 50 includes a pull-up resistor 51 and a transistor 52, and only when the output of the voltage monitoring circuit 30 is at a high level, the transistor 52 is turned on and generates a low level memory protect signal.

As mentioned above, the voltage drop detection voltage of the voltage monitoring circuit 30 is set higher than the voltage drop detection voltage of the voltage monitoring circuit 20, so when transitioning to the memory protect state,
The power supply voltages of the MOS memories do not change at the same time.

Therefore, the data in the CMOS memory will be protected. Also, if the memory is protected, the CMOS
Since the current consumption of the memory is drastically reduced, it is possible to prevent large noise from occurring when switching the power supply.

Although the above embodiment deals with the case where the power supply voltage is positive, it can be similarly applied to the case where the power supply voltage is negative. It is a good idea to choose a large number of them.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, according to the present invention, the detection voltage (
Two different threshold values are set, one is used to control the power supply switching of the CMOS memory, and the other is used to control the power supply switching of the CMOS memory.
By using it for chip select control of a MOS memory, it is possible to reliably protect data in the CMOS memory during a transient state of power supply switching.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of a specific example of the block in Fig. 1, Fig. 3 is an operation waveform diagram of the block in Fig. 1, and Fig. 4 is a conventional memory. A block diagram of the protect circuit, FIG. 5 is an operation waveform diagram of the block in FIG. 4. Explanation of symbols of main parts 1...Main power supply 2...Auxiliary power supply 3...CMOS memory 10...Power switching circuit

Claims (1)

[Claims] A memory protect circuit that protects memory data in the event of a main power supply abnormality, the circuit comprising: power supply switching means for switching to an auxiliary power supply when the absolute value of the voltage of the main power supply is below a predetermined threshold; A memory protect circuit comprising write inhibiting means having a threshold value and inhibiting data writing when the absolute value of the voltage of the main power source is equal to or less than the second threshold value.