JPS6232379U - - Google Patents
Info
- Publication number
- JPS6232379U JPS6232379U JP12339385U JP12339385U JPS6232379U JP S6232379 U JPS6232379 U JP S6232379U JP 12339385 U JP12339385 U JP 12339385U JP 12339385 U JP12339385 U JP 12339385U JP S6232379 U JPS6232379 U JP S6232379U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- duty ratio
- signal
- discrimination
- pulse signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案によるデユーテイ比判別回路の
一実施例を示す結線図、第２図は第１図の動作を
示すタイムチヤート、第３図は従来のデユーテイ
比判別回路の一例を示す結線図、第４図は第３図
の動作を示すタイムチヤートである。
１…積分回路、２…比較回路、３…信号検出回
路。
Fig. 1 is a wiring diagram showing an embodiment of the duty ratio discrimination circuit according to the present invention, Fig. 2 is a time chart showing the operation of Fig. 1, and Fig. 3 is a wiring diagram showing an example of a conventional duty ratio discrimination circuit. , FIG. 4 is a time chart showing the operation of FIG. 3. 1... Integration circuit, 2... Comparison circuit, 3... Signal detection circuit.
Claims (1)
パルス信号を前記積分回路で積分し、この積分値
を前記比較回路で比較し、この積分値が基準値を
超えると判別信号を送出するデユーテイ比判別回
路において、前記パルス信号の有無を検出する信
号検出回路を設け、この信号検出回路が前記パル
ス信号を検出しないとき、この検出回路は前記積
分回路の積分値が前記基準値を超えないように抑
制することを特徴とするデユーテイ比判別回路。 A duty ratio that includes an integrating circuit and a comparing circuit, integrates a periodically input pulse signal with the integrating circuit, compares the integrated value with the comparing circuit, and sends out a discrimination signal when the integrated value exceeds a reference value. The discrimination circuit includes a signal detection circuit that detects the presence or absence of the pulse signal, and when the signal detection circuit does not detect the pulse signal, the detection circuit prevents the integrated value of the integration circuit from exceeding the reference value. A duty ratio discrimination circuit characterized by suppressing a duty ratio.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12339385U JPH0339738Y2 (en) | 1985-08-10 | 1985-08-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12339385U JPH0339738Y2 (en) | 1985-08-10 | 1985-08-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6232379U true JPS6232379U (en) | 1987-02-26 |
| JPH0339738Y2 JPH0339738Y2 (en) | 1991-08-21 |
Family
ID=31014455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12339385U Expired JPH0339738Y2 (en) | 1985-08-10 | 1985-08-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0339738Y2 (en) |
-
1985
- 1985-08-10 JP JP12339385U patent/JPH0339738Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0339738Y2 (en) | 1991-08-21 |
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