JPS6232428B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a watch with a summer time function.

Daylight saving time is the process of moving time forward for a certain period of time to save energy during the summer.
It has achieved energy saving effects in the United States and Europe.

In recent years, various types of watches have been proposed that have the above-mentioned summer time display function added to them.

A conventional watch with a summer time function includes a switch means for changing the daylight savings time time, and the operation of the switch means allows changing to the daylight saving time time. The conventional device here employs a method in which the change to the daylight saving time time is made only after the daylight saving time period actually begins. Therefore, on the first day of daylight saving time, the displayed time before the user performs the switching operation will be displayed later than the standard time (daylight saving time standard time).For example, if an alarm has been set, the alarm will be notified late. A problem arises in which this happens.

In order to prevent the above problem from occurring, it is possible to switch to daylight saving time the day before daylight saving time, but this will cause the problem that the time will be displayed ahead of time on that day compared to the actual time. Put it away.

An object of the present invention is to provide a watch with a summer time function that can display the time of the day without being ahead or behind the actual time even if a daylight saving time switching operation is performed on the day before daylight saving time starts or ends. The goal is to provide the following.

In the present invention, even if an operation is performed to switch from standard time to daylight saving time or from daylight saving time to standard time, the switching operation is not performed immediately, but is performed at the subsequent midnight. .

Hereinafter, the present invention will be explained in detail based on preferred embodiments.

The figure shows a circuit configuration diagram of a timepiece with daylight saving time function according to an embodiment of the present invention.

The oscillator 2 is a highly accurate reference signal source such as a crystal oscillation circuit, and this signal is divided into appropriate frequencies by a frequency dividing stage 4. The minute counter 6 counts the signal from the frequency dividing stage 4 to display minutes. The carry signal from the minute counter 6 is supplied via the second OR gate 8 to an up-down counter 10, which counts to display the hour. This up/down counter 10 can count for 24 hours, and when H or L is applied to the U/D input.
Depending on the signal, up-counting or down-counting is performed. The count states of the minute counter 6 and up-down counter 10 are converted into digital display signals in the decoder/driver 14, and a time display 22 such as hours and minutes is displayed on the display section 20.
will be done.

The switch 30 is a switch means for changing to the daylight savings time time display according to the present invention, and is configured to allow the user to open and close the display. In order to change the time display 22 to summer time time, the switch 30 is closed. When the switch 30 is controlled to close, an H signal is applied to the D input of a flip-flop (hereinafter abbreviated as F/F) 40, thereby setting the Q output 42 to H. This Q output 42 is applied to the D input of the F/F 44 and also to the AND gate 46. and gate 46
The output of the F/F 44 is applied to the other input terminal of the F/F 44. The 32Hz signal O/ ₁ from frequency dividing stage 4 is input to the O/inputs of F/Fs 40 and 44, and therefore F/Fs 40, F/Fs 44 and AND gate 46
When the switch 30 is controlled to close, an on-operation detection signal of a one-shot pulse is outputted from the AND gate 46. In addition, D type F/F5 explained below
The 32HZ signal O/ ₁ from the frequency divider stage 4 is also applied to the O/inputs 6, 58, 60, 72, 74 and 92.

The one-shot pulse output from the AND gate 46 is applied to the O/input of the F/F 48, and the Q output is
will be launched. This H signal is then applied to the AND gate 52 via the first OR gate 50. The carry signal 12, which is the output of the up-down counter 10, is applied to the other input terminal of the AND gate 52. This carry signal 12 is output at midnight, so the output signal 54 is output from the AND gate 52 at midnight. This output signal 54 is applied to the D input of the F/F 56, and then a one-shot pulse circuit composed of the F/Fs 58 and 60 and the AND gate 62 is used to
A delayed pulse 64 of the one-shot pulse is output. The F/Fs 56, 58, 60 and the AND gate 62 constitute a pulse generating circuit 65, and the delayed pulse 64 is applied to the O/input of the up/down counter 10 via the second OR gate 8, where the delay pulse 64 is applied to the O/input of the up/down counter 10, and here the delay pulse 64 is applied to the O/input of the up/down counter 10. Display switching is performed. In other words, a signal obtained by adding 1 to the signal from the minute counter 6 that is supplied as a normal time update is supplied to the O/input of the up-down counter 10, so that the signal obtained by adding 1 to the signal from the minute counter 6 that is supplied as a normal time update is supplied. The time is displayed with the time advanced by one hour (in the embodiment, the time is advanced by one hour during daylight saving time). Specifically, the above-mentioned switch 3
By setting 0 to close, the time display 22 is instantaneously switched to display at 1 a.m. at the first midnight thereafter. Note that the U/D input of the up-down counter 10 is connected to the output 9 of the F/F 92.
4 is applied, and when the output 94 is H, an up count is performed, and when it is L, a down count is performed. As will be described later, when the switch 30 is under close control, the output 94 becomes H, and the up/down counter 1
When the time is 0, an up-count is performed, and a change is made to advance the time by one hour to change the daylight saving time.

Next, a case will be described in which the daylight saving time time display is switched to the normal time display (one hour delayed).
The operation is performed by controlling the switch 30 from closed to open. When the switch 30 is opened, the signal applied to the D input of the F/F 72 via the inverter 70 becomes H. Therefore, the inverter 70,
An off-operation detection circuit 79 composed of F/Fs 72 and 74 and an AND gate 76 outputs an off-operation detection signal 78 of a one-shot pulse. This signal 78 is passed through the OR gate 100 to the F/F
48, and also sets the Q output 82 to H by applying it to the O/input of the F/F 80.
The output 82 is applied to the AND gate 52 via the first OR gate 50, and later, as described above, at the timing of the output of the carry signal 12 of the up-down counter 10, a one-pulse addition pulse is applied to the O/input of the up-down counter 10. applied. However, in this case, the output signal 54 from the AND gate 52 and the F/
Q output 8 where the F80 off operation detection signal is output
The output from the AND gate 90 inputting 2 and 2 is H.
Therefore, the output 94 of F/F92 becomes L,
The up-down counter 10 counts down once only when there is an addition pulse. That is, by switching to the time display delayed by one hour, the change from daylight saving time time to normal time display is achieved.
Here F/F48,80, or gate 100,1
02, the AND gate 104 constitutes a final operation memory holding circuit 105. When the F/F 48 receives the ON operation detection signal from the ON operation detection circuit 47 at its φ input, it outputs the Q output ON operation storage signal to one input terminal of the first OR gate 50, and the F/F 80 outputs the ON operation storage signal from the ON operation detection circuit 47 to one input terminal of the first OR gate 50. When the off-operation detection signal from 79 is received at the φ input, the off-operation storage signal of the Q output is output to the other input terminal of the first OR gate 50. When the OR gate 100 receives the OFF operation detection signal from the OFF operation detection circuit 79, it outputs the output signal to the R input of the F/F 48, and when the OR gate 102 receives the ON operation detection signal from the ON operation detection circuit 47, it outputs the output signal to the R input of the F/F 48. , the output signal is F/F80
output to the R input of According to this, switch 30
Even if it is opened and closed several times at a time due to user's erroneous operation, the last state will always be memorized. Also, the outputs of F/Fs 48 and 80 are both input to the AND gate 104, and the output of either one is L.
When , a memory detection signal that becomes L is output.

On the other hand, the AND gate 90 and F/F 92 constitute a count direction switching circuit 95, and the output count direction switching signal 94 is sent to the up/down counter 10.
is supplied to the U/D input terminal of the

The output signal 64 of the AND gate 62 is also applied to the F/F 68 via an inverter 66. F/
The input signal to F68 is up-down counter 1
The Q output 69 of the F/F 68 is set to H at a timing slightly delayed from the pulse for counting up or down to 0. This inverter 66, F/F6
8 constitutes a memory release circuit 67, and Q output 69
The memory release signal of OR gates 100 and 102
By resetting the F/Fs 48 and 80 via the F/Fs 48 and 80, the subsequent Q outputs of the F/Fs 48 and 80 can be held at L, and unauthorized display switching can be prohibited. Immediately after the F/Fs 48 and 80 are reset, their respective outputs become H, so the AND gate 104 outputs, and the F/Fs 48 and 80 are reset.
F68 is reset and Q output 69 is set to L.
Therefore, at this time, the reset of the F/Fs 48 and 80 is canceled, and subsequent display switching by operating the switch 30 becomes possible.

In this embodiment, the user confirms whether the display is switched to daylight saving time or the operation status is changed by displaying the daylight saving time mark 24 on the display unit 20. This is F/F40
The Q output 42 of is input to the decoder driver 14 for display, and the mark 24 is displayed only when the switch 30 is in the closed state.

As described above, according to the present invention, since the switching operation from standard time to daylight saving time or from daylight saving time to standard time is performed at midnight after the switching operation, the day before daylight saving time starts or ends. Even if a switching operation is performed, the correct time can always be displayed even up to midnight at the time of switching.

[Brief explanation of the drawing]

The figure is a circuit configuration diagram of a timepiece with daylight savings time function according to an embodiment of the present invention. 2... Oscillator, 4... Frequency division stage, 6... Minute counter, 8... Second OR gate, 10... Up-down counter, 14... Decoder/driver, 20
...Display unit, 30...Switch, 47...On operation detection circuit, 50...First OR gate, 52...
AND gate, 65...Pulse generation circuit, 67...
...Memory release circuit, 79...Off operation detection circuit, 9
5...Counting direction switching circuit, 105...Final operation memory holding circuit.

Claims (1)

[Scope of Claims] 1. An oscillator that generates a reference signal, a frequency dividing circuit connected to the oscillator and dividing the frequency of the reference signal, and a frequency dividing circuit connected to the frequency dividing circuit and counting minutes based on the frequency divided signal. a minute counter; an up-down counter connected to the minute counter and counting the hour by a carry signal from the minute counter; an up-down counter connected to the time terminal of the up-down counter and the time terminal of the minute counter; a decoder/driver that converts a time count signal from a counter and a minute counter into an hour display signal and a minute display signal; a display section connected to the decoder/driver that displays the hours and minutes of the time; an external operation switch; an on-operation detection circuit that detects that the externally operated switch is turned on and outputs an on-operation detection signal; and an off-operator that detects that the externally operated switch is turned off and outputs an off-operation detection signal. a detection circuit; upon receiving an on-operation detection signal from the on-operation detection circuit and an off-operation detection signal from the off-operation detection circuit, an on-operation memory signal or an off-operation signal corresponding to the last received signal of both signals; a final operation memory holding circuit that outputs a memory signal; a first OR gate to which an ON operation memory signal output terminal and an OFF operation memory signal output terminal of this final operation memory holding circuit are connected to two input terminals; and this first OR gate. a count direction switching circuit that receives an output signal from the up-down counter and an off-operation memory signal from the final operation memory holding circuit, and supplies a subtraction designation signal to a count direction switching terminal of the up-down counter on the condition that both signals are present; a pulse generation circuit that receives the output signal of the first OR gate and outputs a delayed pulse; and a pulse generation circuit that receives the delayed pulse from the pulse generation circuit together with the carry signal of the minute counter, and sends both signals to the up-down counter. a second OR gate supplied to the clock input terminal; and a memory detection signal indicating that an ON operation memory signal or an OFF operation memory signal is output from the last operation memory holding circuit and a delay pulse from the pulse generating circuit. , a memory release circuit that supplies a memory release signal to a memory release terminal of the last operation memory holding circuit in response to the output of the delayed pulse on the condition that the memory detection signal is present; Upon receiving the midnight signal from the up-down counter and the output signal from the first OR gate, the output signal of the first OR gate is supplied to the pulse generation circuit and the counting direction switching circuit on the condition that the midnight signal exists. A timepiece with a summer time function, characterized in that an AND gate is provided between the output terminal of the first OR gate, the input terminal of the pulse generation circuit, and the input terminal of the count direction switching circuit.