JPS6232453U - - Google Patents

Info

Publication number
JPS6232453U
JPS6232453U JP12178985U JP12178985U JPS6232453U JP S6232453 U JPS6232453 U JP S6232453U JP 12178985 U JP12178985 U JP 12178985U JP 12178985 U JP12178985 U JP 12178985U JP S6232453 U JPS6232453 U JP S6232453U
Authority
JP
Japan
Prior art keywords
parity
word
check
read
added
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12178985U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12178985U priority Critical patent/JPS6232453U/ja
Publication of JPS6232453U publication Critical patent/JPS6232453U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図はこの考案の一実施例を示すブロツク図であ
る。 1a,1b…ダイナミツクメモリ、2…データ
バス、3a…偶数パリテイ生成チエツク回路、3
b…奇数パリテイ生成チエツク回路。
The figure is a block diagram showing one embodiment of this invention. 1a, 1b...dynamic memory, 2...data bus, 3a...even parity generation check circuit, 3
b...Odd parity generation check circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数ワードを並列に読み出し/書き込み可能な
ダイナミツクメモリシステムに対して1ワード単
位でパリテイ生成チエツク回路を設け、データ書
き込み時に1ワードごとに1ビツトのパリテイビ
ツトを付加するとともに、データ読み出し時に1
ワードごとにパリテイチエツクを行なうものにお
いて、複数の上記パリテイ生成チエツク回路とし
て偶数パリテイ用と奇数パリテイ用とを混用した
ことを特徴とするダイナミツクメモリシステムの
パリテイチエツク装置。
For a dynamic memory system that can read/write multiple words in parallel, a parity generation check circuit is provided for each word, and one parity bit is added to each word when data is written, and one parity bit is added to each word when data is read.
A parity check device for a dynamic memory system which performs a parity check for each word, characterized in that a plurality of parity generation and check circuits are used in combination for even number parity and odd number parity.
JP12178985U 1985-08-08 1985-08-08 Pending JPS6232453U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12178985U JPS6232453U (en) 1985-08-08 1985-08-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12178985U JPS6232453U (en) 1985-08-08 1985-08-08

Publications (1)

Publication Number Publication Date
JPS6232453U true JPS6232453U (en) 1987-02-26

Family

ID=31011381

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12178985U Pending JPS6232453U (en) 1985-08-08 1985-08-08

Country Status (1)

Country Link
JP (1) JPS6232453U (en)

Similar Documents

Publication Publication Date Title
JPS6034649U (en) memory access system
JPS6232453U (en)
JPS585133U (en) data transmission system
JPS62117796U (en)
JPS60164252U (en) data processing equipment
JPS59130146U (en) memory device
JPS6074298U (en) Matrix memory system for data conversion
JPH01117000U (en)
JPH0458764U (en)
JPS58147050U (en) information processing equipment
JPS63171844U (en)
JPS60166899U (en) Storage device
JPS58135099U (en) memory device
JPS59155639U (en) memory selection device
JPS58148798U (en) memory element
JPS58118599U (en) Storage device
JPH02138348U (en)
JPS6170243U (en)
JPS6392970U (en)
JPS6211300U (en)
JPH0273258U (en)
JPS60123051U (en) shared memory controller
JPS59112396U (en) data processing equipment
JPS62134151U (en)
JPS59112400U (en) memory device