JPS6232517B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention provides data transmission in which at least one storage device and a plurality of processing devices are connected via a common bus, and data is transmitted between the storage device and the processing devices and between each processing device via the common bus. Regarding equipment. Such a data transmission device is generally referred to as a data transmission system. Further, each processing device may be a computer,
Such a data transmission device (data transmission system) is often referred to as a computer system or a data processing system. As described above, the data transmission device according to the present invention cannot be clearly distinguished from a data transmission system or a computer system, and these are not specifically expressed in this specification. By the way, as computer systems become faster and more distributed, it has become common to use a single shared bus with a parity bit added for data transmission between storage devices (hereinafter referred to as memory) and various processing devices. ing. Conventionally, various processing devices have been provided with parity check means for checking the presence or absence of parity errors, but as the number of processing devices increases, the amount of hardware in this part cannot be ignored. SUMMARY OF THE INVENTION An object of the present invention is to provide a data transmission device that eliminates the need for each type of processing device to have its own error checking means. A feature of the present invention is that one bus monitoring mechanism is provided on the common bus, and this bus monitoring mechanism detects a transmission error on the common bus, and when an error is detected, at least data transmission is performed. Error information is sent to the processing device. Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an example of the overall configuration of a data transmission device according to the present invention. In FIG. 1, 10 is a memory, 11 is a bus monitoring mechanism, 12 (12-1 to 12-3) are various processing devices, 13 is an address bus, 14 is a data bus, 1
5 is a response bus, and 16 is an error notification signal line. The various processing devices 12 effectively use the three buses mentioned above to transmit data to and from the memory 10. The table below shows how each bus is used.

[Table] Here, ○ indicates use.
As shown in the table above, the data write request of a, the data write response of b, the data read request of c and its response of d, and the data write response of b and the data read request of c. Since the combinations use different buses, they can be performed simultaneously in the same time slot. Figure 2 shows a time chart of the simultaneous operations. At time slot i, a memory read request is output from one of the various processing devices 12 to the memory 10 via the address bus 13. At time slot i+1, a memory write request is further outputted via address bus 13 and data bus 14 from one of the various processing devices 12-2. At time slot i+3, the response at time slot i is returned via the data bus 14 and response bus 15, and at this time, it is also possible to output a memory read request via the address bus 13. At the next time slot i+4, the response from time slot i+1 is output via the response bus 15, and at this time, a memory write request can be output. In occupying each bus as described above, the occupancy control method is the key. Possible occupancy control methods include a centralized type in which the information is held in one place in the system, and a distributed type in which the information is distributed among various processing devices and memories, but the latter method will be explained here. FIG. 3 is a diagram showing the details of the occupancy control circuit 17 in the various processing devices 12 and the relationship with the external interface. When the device 12 becomes the source of each data, it sends a read request (RREQ) 113, one time slot before the transfer, depending on the type of the request.
Write request (WREQ) 114, read answer request (RANS) 115 write lancer request (WANS)
116 is output. Gate 133, 134, 13
5 converts the above request signal into an address bus occupancy request signal 130, a data bus occupancy request signal 131, and a response bus occupancy request signal 132 using the logic shown in the following table.

[Table] Individual request signals are also output from other devices, and these are sent to the occupancy control circuit 17 as an address bus occupancy request signal 13-1, a data bus occupancy request signal 14-1, and a response bus occupancy request signal 15-1. sent to. In the occupancy control circuit 17, the request signal receiving section 1
At 00 to 102, each request signal is received, and only requests from the device are taken into the occupancy control circuit according to the priority given in advance. The output signals 103-105 of the request signal receiving units 100-102 are sent to the gates 106-108.
This checks whether a request is being output from a device with a higher priority. A request is not output from a device with a higher priority, and the request signal 130~ from the own device
If 132 is active, gates 109-11
2 works. Furthermore, the following checks are performed by gates 117-120. (1) If the request is a read request and occupation of the address bus is permitted by gate 109, gate 117 operates. (2) If the request is a write request and occupation of the address bus and data bus is permitted by gates 109 and 110, respectively, gate 118 operates. (3) If the request is a read answer and occupancy of the data bus and response bus is permitted by gates 110 and 111, respectively, gate 119 operates. (4) If the request is a write answer and the occupation of the response bus is permitted by gate 111, gate 120
works. The outputs of gates 117-120 are sent to register 12.
1, at the end of the time slot, the clock signal 12
Set by 6. The above processing is performed one time slot before the transfer, and in the transfer time slot, it corresponds to the output signal of the register 121, and when the read request transfer permission signal 122 is output, it is preset in the address signal bus 13-2. The contents of address register 127 are output. Also, when the write request transfer permission signal 123 is output, the address register 127 and data register 128
The contents of are output to the address signal bus 13-2 and data signal bus 14-2, respectively. Furthermore, when the read response transfer permission signal 124 is output,
The contents of data register 128 and response register 129 are output to data signal bus 14-2 and response signal bus 15-2, respectively. Furthermore, when the write response transfer permission signal 125 is output, the contents of the response register 129 are
It is output to 5-2. As mentioned above, depending on the type of data transmission,
Since only the bus to be used is occupied, it is possible to perform data transmission using a bus that is not occupied by other devices with a lower priority level, and it is possible to improve bus throughput. In the embodiments described above, a method has been described in which data transmission between various processing devices and between various processing devices and memory is considered equally, and therefore a method is provided in which response lines from the various processing devices are occupied. However, in general, in the configuration shown in FIG. 1, memory requests from various processing devices and responses from the memory account for most of the load. Therefore, holding the response bus occupancy request signal 15-1 individually will lead to an increase in the number of signal lines as the number of various processing devices 12 increases. The following relationship shows the general frequency of use of each bus.

[Table] For this reason, for the response bus, a dedicated request line is set up for frequently used memory.
For various processing devices that are used less frequently, a method of sharing the data bus occupancy request line may be considered. The output method of the above-mentioned occupancy request line is shown in the following table.

[Table] Also, the priority order between memory and various devices is set so that memory has a higher priority. When the above method is adopted, data bus occupancy request signal bus 14-1, response bus occupancy request signal bus 1
Since the connection relationship of 5-1 is complicated unlike that shown in FIGS. 1 and 3, it is shown in FIG. Similarly to FIGS. 1 and 3, the memory 10 outputs the DBRQO signal 151 when occupying the data bus, and outputs the ACKRQO signal 155 when occupying the response bus. However, the various processing devices 12 have data buses,
When it is desired to occupy any of the response buses, one occupancy request signal DACKRQi 152 to 154 of the occupancy request signal group 156 assigned to each processing device is used.
(i=1 to n) is output. On the other hand, the occupancy control circuit 17 of each processing device has a configuration as shown in FIG. The difference from FIG. 3 is that among the request signal receiving sections 100 to 102, the data bus request signal receiving group 101 and the response bus request receiving section 102 receive the request signal 151 from the memory,
155 are input individually, but a group of occupancy request signals 156 from various processing devices are input in common. Also, in the output section of the request signal, the gate 1
50, the data bus request signal 131 and the response bus request signal 132 are logically summed and output. With the above method, the number of request lines from various processing devices can be reduced to two, the address bus request line 130 and the data and response bus request line 154, and data transfer between memory and various processing devices can be achieved. It is possible to efficiently use the address bus, data bus, and response bus depending on the type of data transfer. What has been described above is that no matter which occupancy control method is adopted, the register 121 of the occupancy control circuit shown in FIGS. Information is set. Next, the procedure for permitted information transfer will be explained. Although the content of the data to be transferred differs depending on the type of transfer, the transfer procedure is the same. Here, the procedure will be explained using the transfer of a data write request as an example. FIG. 6 shows details of the structure of the data transfer registers on the sending side and the receiving side and the bus monitoring mechanism that performs error checking. Here, a situation is shown in which a memory write request is output from various processing devices 12 to the memory 10. When the various processing devices 12 obtain exclusive rights to the address bus 13 and data bus 14, the various processing devices 12 register 121
For example, 123 is set to 1 among the transfer permission signals 122 to 124 output from the transfer permission signals 122 to 124. Therefore, the gates 203 and 205 in the address register 127 and data register 128 operate, and the internally stored data are sent to the address signals 13-2 and 13-2, respectively.
Output to data signal 14-2. The address signal 13-2 is a startup function signal 13-2-1, a request source device number signal 13-2-2, and a memory address signal 13, depending on its contents.
- Divided into 2-3. On the memory 10 side, the sent activation function signal 13-2-1 is decoded by gates 212 and 213, and if the activation function is memory activation, the gate 212 operates and the address signal 13-2-1 is decoded by gates 212 and 213.
2 in the corresponding registers 208, 209, and 210. Further, when the activation function is a memory write, the gate 213 operates and sets the data signal 14-2 in the register 211. On the other hand, address signal 13-2, data signal 14
-2 is output with parity added to improve reliability. Parity checking is performed by the address signal check circuit 206 and data signal check circuit 207 provided in the bus monitoring mechanism 11 in the following procedure. The address signal check circuit 206 takes in the address signal 13-2, performs a parity check for each time slot, and sends the check results to the memory 10 and all the various processing devices 12.
It is sent as an address parity error signal 220. The memory and various processing devices that have transmitted and received address data using the address signal 13-2 check the address parity error signal 220 to determine whether the transmission and reception were performed correctly. On the other hand, the data signal check circuit 207 also takes in the data signal 14-2, performs a parity check for each time slot, and sends the check results to the memory 10 and all the various processing devices 12.
It is sent as a data parity error signal 221. The memory and various processing devices that have transmitted and received data using the data signal 14-2 check the address parity error signal 221 to determine whether or not the transmission and reception were performed correctly. As the above-mentioned determination control method, the following methods can be considered depending on the type of data sent.

[Table] Note that all of the above methods are performed on the receiving side, and no special processing is performed on the transmitting side. A method for implementing the above system will be explained using FIG. 6. Memory 10 receives memory requests into registers 208-211 through the operation of gates 212 and 213. Gate 212 is simultaneously connected to flip-flop 3.
00 and 301 are operated to output an address parity error signal fetch and a memory activation signal, respectively. Further, the gate 213 is connected to the memory 10
Since this is a write request to the flip-flop 302, a data parity error is also set in the flip-flop 302. The outputs of flip-flops 301 and 302 are logically summed at gate 303, and when an error occurs, gate 304 outputs a start signal 13 to memory 309.
4 is not output and the process is aborted. On the other hand, when an error occurs, the gate 305 outputs a buffer 306 for outputting the request source device number and an end signal buffer 307 to the response bus 15-2. The end signal register 307 contains the error signal 3.
15 has been sent, the requester is notified that an error has occurred. On the other hand, at the time of normal termination, a termination signal 316 is output from the memory 309, which causes the gate 30
5 operates, and the buffer 306 and end signal buffer 307 are output to the response bus 15-2. Further, during memory reading, the data buffer 308 also operates, and the read data is also output as the data signal 14-2. These data are checked by response signal check circuit 230 and data signal check circuit 207. The response parity error 222 and data parity error 221 are set in the flip-flops 310 and 311 by the operation of the control circuit 312 in the various processing devices 12 having the same number as the request source device number, and the set contents are stored in the end signal register. 31
3, it is added to the error information. This allows error information on the bus to be transmitted to the request source without contradiction. As described above, by integrating and performing checks on the bus in one place, and by allowing the transmitting and receiving units to receive only the error check results, there is no need for each unit to have an individual error check circuit. It is possible to reduce the amount of hardware.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the overall configuration of a data transmission device according to the present invention, FIG. 2 is a time chart of an example of data transmission, and FIG. 3 is a diagram showing various processing devices connected to the data transmission device. Figure 4 is a diagram showing the relationship between the internal occupancy control circuit and the external interface, Figure 4 is a diagram showing the connection relationship of request signals when the request signals of each bus are reduced according to the request frequency, and Figure 5
This figure shows the structure of the occupancy control circuit corresponding to FIG. 4, and FIG. 6 shows the details of the structure of the data transfer registers on the sending side and the receiving side and the bus monitoring mechanism. 10...Memory, 11...Bus monitoring mechanism, 12
... Various processing devices, 13 ... Address bus, 14
...Data bus, 15...Response bus, 16...Error notification signal line.

Claims (1)

[Claims] 1 At least one storage device and a plurality of processing devices are connected to a common bus, and data is transmitted between the storage device and the plurality of processing devices via the common bus. includes at least an address bus for transmitting the address of the storage device, a data bus for transferring data to be written to the storage device and data read from the storage device, and a response bus for transferring the write and read response signals. and a bus monitoring mechanism for detecting transmission errors on the address bus and data bus is connected to the common bus, and the bus monitoring mechanism detects transmission errors when valid information is being sent to the address bus and data bus. The system checks for errors and sends the check results to the error notification signal line commonly connected to the storage device and each processing device.The storage device that has received the error notification responds when the transferred data is requested data. A data transmission device characterized in that error information is returned as data to a processing device of a transfer source.