JPS6232551A - Memory access system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] In a device equipped with a plurality of ports that can access memory simultaneously based on access by a processor (MP), a large-capacity buffer that stores data fetched from the memory is provided. By comprising a memory and an address register that allows the processor to store a write destination address for the buffer memory,
When the processor (MP) accesses the memory, it simply writes the write destination address for the buffer memory in the address register in accordance with the access port number, and when the memory access ends, the memory is fetched by the memory access. The fetched data is accessed based on the port number, the address of the buffer memory to which the data is to be written is recognized, and the fetched data is written from the area of the address in the buffer memory. This is what I did.

[Industrial application field]

The present invention provides a memory access method for an apparatus equipped with a plurality of ports (A-D) that can access memory simultaneously based on access by a processor (MP), and a buffer memory that stores data fetched from the memory. Regarding.

With the recent spread of computer systems, the amount of data to be processed is increasing, and efficient data processing is required.

However, with the recent remarkable progress in semiconductor technology, the speed of processors (MP) has been increased, but at the same time, the capacity of memory has also been increased, so the burden on memory access from the processor has increased. There is a trend towards becoming heavier.

In particular, in a computer system that has multiple devices, each of which has multiple memory access ports that can access memory at the same time, a specific job executed by a device is , Even if you try to access memory using a free port, if all ports are busy, the fetch data stored in the port will be fetched in response to the memory access requested by another job, and then If the new memory access has to be performed and the buffering capacity is limited by the number of ports, there is a problem that the access frequency increases and the overhead in the processor (MP) increases.

Also, if memory access is performed simultaneously from multiple devices or multiple ports, the order of responses to each memory access cannot be guaranteed, so it is necessary to fix the access port for a specific job. There is a problem that cannot be done.

Under these circumstances, there has been a demand for a system that can effectively perform fetch access to memory even in computer systems equipped with a plurality of memory access ports.

[Conventional technology]

FIG. 2 is a diagram illustrating a conventional memory access method.

First, when a memory access request is sent from the processor (MP) 1 of the device, a port control unit (not shown) searches for the number of an empty port, and
MP) Returns the port number to 1.

When the processor (MP) 1 performs memory access by controlling the selector (SEL) 50 based on the received port number, memory access information (for example, data, address, command, etc.) is transferred to the corresponding port. The memory request control unit (MRC) 31 is activated.

The acid memory request control unit (MRC) 31 adds a memory access request number (ID) to the memory access information.
is added to the memory control unit (MCU) 3 to access the main storage device (memory) not shown.

When the fetch data is returned from the main storage unit W (memory) together with the memory access request number (10), the memory request control unit (MRC) 31 performs a process based on the memory access request number (ID). recognizes the port number of the access request source and connects the port (A-D)2.
Fetch data is stored in a fixed capacity buffer memory provided within the device.

After that, the fetch data is sent to a selector (SEL) 51
is transferred to the processor (MP) 1 at a specific write timing (WT).

[Problem that the invention seeks to solve]

Therefore, in the conventional method, for memory access from processor (MP) 1, the storage location of fetch data corresponding to 8 memory accesses is
Since it is stored only for port (A-D) 2 selected when MP) 1 performs memory access, in order for the concerned processor (MP) 1 to import the data, the data must be stored at the time of the memory access. I needed to know the port number.

In addition, since the number of memory access ports (A-D) 2 provided for each processor (MP) 1 is limited, the maximum number of memory access ports (A-D) 2 provided for each processor (MP) 1 is (A-D) Only the fixed capacity buffer area provided in 2 can buffer fetch data, so even if there is a lot of fetch data from a certain job and a new memory access request occurs immediately, , each port) (A to D) 2 is busy, the fetch data stored in each port must be fetched into each job, and the processor (MP
) There was a problem that the overhead in 1 increased.

In addition, the memory access ports (8 to D) 2 are shared by multiple jobs executed by the processor (MP) 1, for example, so when trying to capture a free port in a certain job, the memory access ports (8 to D) 2 are not necessarily the same ports. Therefore, when focusing on a specific job executed by processor (MP) 1, there was a problem in that the port to be captured could not be specified.

Furthermore, in this computer system, since the memory is accessed by multiple devices, each processor (heart)
■There is a problem in which the order of responses cannot be guaranteed for memory accesses from specific jobs executed by The problem was that it wouldn't work.

This increases the burden on the processor for memory access.

In view of the above-mentioned conventional drawbacks, the present invention provides a memory system in which the storage location of fetch data is made floating with respect to the above-mentioned ports in a device equipped with a plurality of memory access ports, and the orderliness of responses to memory accesses is not guaranteed. The purpose of this invention is to provide a method for improving the performance of a processor (MP) when using a processor (MP).

[Means for solving problems]

In the present invention, a buffer memory (42) that stores data fetched from memory is provided in a device equipped with a board (A-D) 2 that can simultaneously access memory based on access by a processor (MP) 1.
) and the buffer memory (42) for the fetch data.
The write destination address for the processor (MP)
1 to an address register 41 that can store data in units of 2 ports (A-D), and performs memory request control at the end of the memory access based on the memory access request from the processor (MP) 1. Department (
MRC) 31, the above ports (A-D)
From the area specified by the contents of the address register 41 accessed by the port number (CPN0) corresponding to 2,
The fetch data is configured to store a predetermined amount of the fetch data.

[Effect]

That is, according to the present invention, in a device equipped with a plurality of port numbers that can access a memory simultaneously based on access by a processor (MP), a large capacity buffer memory for storing data fetched from the memory is provided. , and an address register in which the processor can store a write destination address for the buffer memory, so that when the processor (MP) accesses the memory, the write destination address for the buffer memory is stored in accordance with the access port number. By simply writing the write destination address to the address register, at the end of the memory access, the data fetched by the memory access is accessed based on the port number and stored in the buffer to which the data should be written. Since the memory address is recognized and the fetch data is written from the area of the address in the buffer memory, the storage location of the fetch data can be made floating with respect to the port, and the processor Processor (when using a memory system that does not guarantee the order of responses to memory accesses from (MP)
This has the effect of improving the performance of MP.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, the same reference numerals as in FIG. 2 indicate the same objects, and address registers 41. Buffer memory 42 and its associated mechanisms are the functional blocks necessary to implement the present invention.

First, from processor (MP) 1 to free ports (A-D
) 2, the address register 41 is accessed according to the port number set in the port number register (RQPN) 60, and the area corresponding to the port (A to D) 2 is accessed. In addition to writing the address where the fetch data should be stored, the selector (SEL) 50 is controlled by the output of the port number register (RQPN) 60, and memory access information 1 (data .

addresses, commands, etc.), and the memory request control unit (
Activate MRC) 31. The above command determines, for example, the amount of data to be fetched in l memory access.

When the memory request control unit (MRC) 31 recognizes a memory access request from each port (A to D) 2, it adds a memory access request number (ID) to the memory access and performs memory control. Unit (gate C0)
Send to 3.

In the memory control unit (MCU) 3, after performing conflict control with memory accesses from other devices, such as channel devices, when memory access from the processor (MP) 1 is selected, a main controller (not shown) is selected. A storage device (memory) is accessed, and the fetch data returned together with the memory access request number is sent back to the memory request control unit (MRC) 31 described above.

The memory request control unit (MRC) 31 determines the port number (C) corresponding to the memory access request number (ID).
When the port number (CPN0) is recognized, the above fetch data is stored in the port (A-D)2, and the port number (CPN0) is recognized.
0), by accessing the address register 41, the fetch data write address in the buffer memory 42 corresponding to the port (A-D) 2 is read, and the buffer memory 42 is accessed based on the address. be done.

At this time, the selector (SEL) 51 is controlled by the port number (CPN0), and the port number (8 to D) is controlled by the port number (CPN0).
) If 2 is selected, the aforementioned fetch data is read out at a specific write timing (WT), and a predetermined amount of data determined by the aforementioned command is stored from the aforementioned write address of the buffer memory 42.

Therefore, as shown in the figure, when the processor (MP) 1 performs memory access, the fetch data can be read from the buffer memory 42 at the buffer memory address specified by the processor (MP) 1, unlike the conventional system. There is no need to be aware of port numbers, and the burden on memory access can be reduced.

Furthermore, by increasing the capacity of the buffer memory 42, the amount of buffering of fetch data required by each job executed by the processor (MP) 1 can be increased, thereby reducing the frequency of memory access requests. As a result, the performance of the processor (MP) 1 can be improved.

In this way, in the present invention, when performing memory access in a device equipped with a plurality of memory access ports, when an empty port is acquired, the address of the buffer memory that the user wants to use is assigned based on the port number. The feature is that by writing to the register, subsequent reading of fetch data can be performed using the address of the buffer memory, regardless of the port number.

〔Effect of the invention〕

As described above in detail, the memory access method of the present invention is capable of fetching data from a memory in a device equipped with a plurality of ports that can access memory simultaneously based on access by a processor (MP). By providing a large-capacity buffer memory for storing a memory and an address register in which the processor can store a write destination address for the buffer memory, when the processor (MP) accesses the memory, the access By simply writing the write destination address for the buffer memory in the address register in accordance with the port number, at the end of the memory access, the data fetched in the memory access will be written to the address based on the port number. Since the register is accessed and the data is written to, the address of the couch memory is recognized and the fetch data is written from the area of the address in the buffer memory, the storage location of the fetch data is It can be made floating with respect to a port, and has the effect of improving the performance of the processor (Mr') when using a memory system that does not guarantee the order of responses to memory accesses from the processor (MP). .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a diagram illustrating a conventional memory access method. In the drawings, 1 is a processor (MP), and 2 is a port (A-D). 3 is a memory control unit (MCU). 31 is a memory request control unit (MRC). 41 is an address register, and 42 is a buffer memory. 50.51 is a selector (SEL). are shown respectively.

Claims (1)

[Claims] Based on the access by the processor (MP) (1),
In a device equipped with a plurality of ports (A to D) (2) that can access memory simultaneously, a buffer memory (42) stores fetch data from the memory, and the buffer memory (42) stores the fetch data. ) is provided with an address register (41) capable of storing a write destination address from the processor (MP) (1) to the ports (A to D) (2) in units of the processor (MP) (1). ) at the end of the memory access based on the memory request from the buffer memory (4).
To write the above fetch data to 2), write the port number (CPN0) corresponding to the above ports (A to D) (2).
A memory access method characterized in that the determination is made according to the contents of the address register (41) specified by the address register (41).