JPS6232560A - Data transmission system - Google Patents

Abstract

PURPOSE:To improve efficiency of use of a standard bus by adding a latch for data-holding to an information processor wherein the data of short word- length are processed thereby to latch the data of word-length difference when executing data transmission and by transmitting the latched data along with the last data when transmitting the last data. CONSTITUTION:The latch 1a and a buffer 2a in an I/O controller 4a are used for transmitting a data of high-order eight bits while the latch 1b and a buffer 2b are for transmitting a data of low-order eight bits. When the I/O controller 4a inputs the data of a memory board 4b, the high-order-eight-bit data and the low-order-eight-bit data are inputted by an RD signal from a data bus 3a, and the former data is latched but the altter one is internally processed. The standard bus is, at this point of time, is made free. Then the latched data is internally processed. When outputting, the low-order-eight-bit data is latched and then is outputted with the high-order one into the data bus 3a by a WR signal. However, the data bus 3a is made free as long as the low-order-eight-bit data is being latched.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer method for transferring data between information processing devices using a common standard bus.

[Conventional technology]

In conventional data transfer methods, when multiple information processing devices transfer data with different word lengths on a common standard bus, the information processing device that handles data with a long word length transfers information processing that handles data with a short word length. Data transfer was performed by matching the word length of the data to the device.

That is, an information processing device that handles data with a long word length divides the data and transfers the data in accordance with an information processing device that handles short data.

[Problem that the invention seeks to solve]

Therefore, the conventional data transfer system has the drawback that the number of data transfers increases in an information processing apparatus that handles data with a long word length, which reduces the efficiency of using the standard bus.

[Means for solving problems]

In order to solve the drawbacks of the prior art, the data transfer method of the present invention adds a latch for holding data to an information processing device that handles data with a short word length, and when transferring data, it handles data with a difference in word length. The latched data is also transferred when the last data is transferred, and the data transfer is performed in accordance with the information processing device that handles data with a long word length.

Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

3a is a standard data bus, 4a is an I10 controller that handles 8-bit data, 4b is a memory board that handles 16-bit data, and 3b is a data line inside the I10 controller 4a. La and 1b are latches for data retention, and 2a and 2b are buffers, which are installed in the I10 controller 4a.

110 Latch 1a and buffer 2a in controller 4a
is used to transfer upper 8 bit data, and latch 1b and buffer 2b are used to transfer lower 8 bit data.

First, the I10 controller 4a
The operation when reading 6-bit data as 8-bit data will be explained.

The 16 bits 1 to 1 of the memory board 4b are data bus 3.
The upper 8 bits 1 through data are latched by the latch 1a, and the lower 8 bits are internally processed through the buffer 2b and the data line 3b. At this point, the data bus is unused, and the upper 8-bit data is internally processed through the data line 3b after the lower 8-bit data is internally processed within the I10 controller 4a.

Next, the I10 controller 4a is connected to the memory board 4b.
This section explains the operation when writing cut data. The first 8 bits of data from the data line 3b are stored in the latch 16 as the lower 8 bits.
However, the data bus is unused because it is inside the I10 controller 4a. The 0th order 8 bit data passes through the buffer 2a as upper 8 bit data, but at this time, it is latched into the latch 1b first. The data is output to the data bus 3a as 16-bit data, and the data is written to the memory board 4b. however,
When transferring 16-bit data, data processing differs depending on how many bytes of data are transferred and from which memory address. In the above example, when the start address of the memory is an even number and the number of data is an even number, when the start address is an odd number and the number of data is an odd number, the first data of data transfer is transferred. If the start address is an odd address and the number of data is an even number, the first and last data must be transferred as 8-bit data.In this case, the input/output of the I10 controller 4a In this case, latches 1a and 1b are not handled, and data is transferred through buffer 2a when outputting upper 8-bit data and through buffer 2b when inputting/outputting lower 8-bit data.

Next, the operation of one embodiment of the present invention will be explained with reference to FIGS. 29 and 3. FIG. 2 shows the timing when the I10 controller 4a in FIG. FIG. 3 is a timing diagram of a data bus. The upper 8-bit data and lower 8-bit data in FIG. 2 are input from the data bus 3a from the RD scratch signal.
The upper 8 bit data is latched and the lower 8 bit data is internally processed. The standard bus becomes unused at this point.

Subsequently, the upper eight bit data captured in the latch are internally processed.

FIG. 3 shows the timing when the I10 controller 4a in FIG. 1 outputs data from the memory board 4b, FIG. 3(a) is a timing chart on the I10 controller I/roller 4a, and FIG. 3(b) is a timing diagram of the data bus.

The lower 8 bit data of the 37th (a>) is latched and then output to the data bus 3a by the WR signal together with the upper 8 bit data, but while the lower 8 bit I data is latched, the data bus 3a is It becomes unused.

〔Effect of the invention〕

As explained above, in the present invention, by providing a latch in a standard bus port that uses 8-bit data, it is possible to convert 8-bit data into 16-bit data during data transfer. unused time increases. Therefore, there is a high chance of acquiring the information when another information processing device requests its use.

This leads to an improvement in the throughput of the entire system.

Although the explanation has been made assuming that the data is 8 bits and 16 bits, other combinations are also possible by providing latches to compensate for the difference in data length.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2(a)
,(b), FIGS. 3(a) and 3(b) are timing diagrams showing the operation of FIG. 1. ], a, 1b...Latch, 2a, 2b...Buffer, 3a...Standard data bus, 3b...Data line, 4
a...I10 controller, 41]...memory board. Agent Patent Attorney Uchihara Mukaya 1 Figure fa, Ib---Rack + 2 cl
, 21)----)

Claims (1)

[Claims] In a data transfer method in which multiple information processing devices that handle data with different word lengths use a common standard bus, the information processing device that handles data with short word lengths has a A data transfer method characterized in that a latch is added to match the word length of the information processing device to an information processing device that handles data with a long word length.