JPS6232629B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device having a preferable contact structure.

A conventional technique for connecting a lower electrode layer and an upper electrode layer is as follows. That is, a first insulating film is formed on a semiconductor substrate using, for example, a thermal oxide film, a lower electrode layer is formed on top of this, and
coated with a second insulating film of CVD oxide film;
A contact hole smaller than the width of the lower electrode layer was formed in the insulating film, and then an upper electrode layer was formed that extended over the second insulating film and connected to the lower electrode layer through the contact hole. .

One of the reasons for providing a contact hole smaller than that of the lower electrode layer is to prevent the upper electrode wiring layer from breaking. In other words, if a contact hole is formed that is larger than the width of the lower layer electrode and all the upper and side surfaces of the lower layer electrode are exposed, this layer has a large cross-sectional shape, so the large stepped portion This is because there is a risk that the upper electrode layer may break due to this. In this regard, if a small contact hole is provided, the area around the second insulating film above the contact hole can be made gentle and the second insulating film can be made thinner.
Since the upper electrode wiring layer is connected only to the upper surface of the lower electrode layer from above the second insulating film through the gentle upper periphery of the contact hole, there is no concern about the above-mentioned disconnection.

However, such a small contact hole does not provide a sufficient contact area. On the other hand, for this purpose, it is also conceivable to enlarge the contact area of the lower electrode layer and to make the contact hole smaller than this contact area, but with a sufficient contact area. However, in this structure, a part of the lower electrode layer, that is, the contact area, is large, which prevents high density, and also increases the additional capacitance for this electrode, which prevents high speed.

An object of the present invention is to provide an insulated gate field effect transistor that enables high-density and high-speed operation, provides a predetermined contact area, and prevents the word line, which is the upper layer electrode wiring, from being cut. An object of the present invention is to provide a semiconductor device including a memory cell having a connection structure in which the transistor and a capacitive element are coupled.

A feature of the present invention is that a girder line extends in one direction in a planar shape, a word line extends in a direction perpendicular to the one direction, and one of the source and drain regions of the insulated gate field effect transistor is connected to the girder line. A capacitive element coupled to the transistor is provided between the transistor and a thick insulating film selectively provided on the semiconductor substrate, and the word line is connected to the gate electrode of the transistor and is connected to the capacitive element. In the semiconductor device extending in the perpendicular direction, a thermal oxide film is deposited on the sides of the gate electrode, and the upper surface of the gate electrode above the operating area of the transistor is in the width direction. The word line has an exposed surface exposed in all of the perpendicular directions, and the word line is connected to the entire width of the upper surface of the gate electrode on the operating area through the exposed surface; is a semiconductor device extending from above the thermal oxide film onto the capacitive element in a direction perpendicular to the plane shape.

According to such a configuration, the entire width of the lower gate electrode portion is exposed in a certain direction, so a sufficient contact area can be obtained, and a large contact area is not required. High density and high speed can be achieved. Furthermore, due to the presence of the side oxide film, the stepped portion of the lower layer gate electrode becomes smaller, thereby preventing step breaks in the upper layer word line. Moreover, since the oxide film on this side portion is a thermal oxide film of good quality, sufficient insulation between the word line in the upper layer and the semiconductor substrate is maintained.

Next, in order to better understand the present invention, embodiments of the present invention will be described using figures.

FIG. 1 is a plan view of a conventional integrated circuit. This integrated circuit represents a one-transistor type memory obtained through the manufacturing process of a silicon gate type MOS integrated circuit. A memory cell is formed at the intersection of a column line 102 of an opposite conductivity type region formed inside a semiconductor substrate 101 of one conductivity type and running in a vertical direction, and an aluminum word line 103 running horizontally through a surface protective film of the substrate 101. It consists of a transistor 110 having a gate electrode 104 in the lower layer of crystalline silicon, and a capacitive element 120 obtained by a power supply wiring electrode 105 made of polycrystalline silicon. A channel region of transistor 110 is located beneath gate electrode 104 between opposite conductivity type region 102 and opposite conductivity type region 106 . Opposite conductivity type region 10 on the side of capacitive element 120 via the gate electrode
6 is a connection region between the transistor 110 and the capacitor 120. Upper layer word line 103 and gate electrode 1
04 is obtained through an aperture 107 on a large contact region 109 of the gate electrode remote from the channel region of the gate electrode, so that the conventional memory cell occupies only a small area per memory cell. Becomes large.

FIG. 2 is a plan view of an embodiment of the present invention.
In this embodiment, a transistor 210 is formed at the intersection of the opposite conductivity type region 102 of the beam line and the gate electrode 201 in the lower layer of polycrystalline silicon, and an opening 202 is provided directly on the channel region of this transistor 210. Note that the width of the gate electrode 201 and the opening 20
2 have the same width as shown in FIG. 3F below. Transistor 210 and capacitor 22
There is a region 106 of the opposite conductivity type common to 0. A word line 103 of the upper layer of aluminum passes through the upper surface of the gate electrode 201, and this word line 103 therefore passes primarily over the active region, reducing the ineffective area. Word line 103 and gate electrode 20
The opening 202 that obtains conductive coupling with the gate electrode 2
01 is a self-aligned aperture on the top surface. Note that this gate electrode 201 and the opening (contact hole) 20
As is clear from Figure 3 below, the sizes of 2 are the same. Polycrystalline silicon as gate electrode material,
A conductive material with a high melting point such as molybdenum or tungsten can be used.

FIGS. 3A to 3F are cross-sectional views of samples in each step of a manufacturing method according to an embodiment of the present invention. This manufacturing method uses a known silicon nitride film as an oxidation-resistant mask material for selective thermal oxidation, and as shown in FIG. Formed on the surface of All of these surface oxide films are SiO ₂ films formed by thermal oxidation from the substrate, and the thickness of the peripheral oxide film 301 is 1 to 1.5 μm.
The thickness of gate oxide films 302 and 303 is about 500 Å. The substrate 304 has a concentration of 5×10 ¹⁵ cm ⁻³ and has a P-type region 305 directly under the peripheral oxide film 301 with a surface concentration of 10 ¹⁶ to 10 ¹⁷ cm ⁻³ . This sample is then grown on the surface of phosphorous-doped polycrystalline silicon with a thickness of about 0.5 μm and silicon nitride film with a thickness of 300 to 1000 Å, and etched through a photoresist process to form gate electrodes 306, 307 and the like as shown in FIG. 3B. A power supply wiring electrode 308 is formed. These electrodes are approximately 10 ²⁰ cm ^-3
It is made of polycrystalline silicon containing phosphorus, and a SiO ₂ layer of several hundred Å thick is provided on the top surface as necessary.
Silicon nitride films 309, 310, 31 through the film
1 is coated.

Next, as shown in FIG. 3C, phosphorus is introduced into the sample using each electrode and the surrounding oxide film as a mask to form N-type regions 312, 31 with a surface concentration of 10 ²⁰ to 10 ²¹ cm ^-3 .
3,314,315 are formed. This N-type region 3
12 to 315 are the digit lines in FIG. 2, N-type regions 312 and 315 that operate as one of the drain or source of the transistor, the other drain or source of the transistor, and the capacitor 220.
N-type region 313,3 which operates as one terminal of
Consists of 14. Of the N-type region formation, wiring electrode 3
The silicon nitride film on the upper surface of 08 is removed. The sample is then thermally oxidized to form N-type regions 312-31.
At the same time as pushing in the wiring electrode 308 and each N-type region 312 to 315,
SiO ₂ film 316, 317, 318, 319, 32
form 0. Even in this oxidation process, the gate electrode 30
Silicon nitride film 309, 31 on the top surface of 6, 307
0 is not substantially oxidized, and a thermal oxide film 316 is grown by selective oxidation only on the upper surface of the wiring electrode 308, as shown in FIG. 3D. Thereafter, the silicon nitride film of the sample is removed to expose the upper surfaces of the underlying gate electrodes 306 and 307, as shown in FIG. 3E. The silicon nitride film is selectively removed by uniformly treating the sample by utilizing the fact that the etching action of hot phosphoric acid or plasma is more dominant than that of SiO ₂ .

Finally, the sample is completed by forming the required upper layer word line 321 through aluminum vapor deposition and photoresist process on the aluminum vapor deposited layer, and providing lead-out electrodes 322 from the substrate 304. word line 32
1 extends laterally at right angles to the vertically extending N-type regions 312, 315 and is conductively coupled to the exposed surface of the gate electrodes 306, 307 on the channel region of each transistor.

According to the manufacturing method of the above-described embodiment, the exposed surface of the gate electrode is obtained by a self-manufacturing method by selective etching of the silicon nitride film. This can be achieved reliably and safely even for gate electrodes with a large area. or,
Since the area occupied by the obtained integrated circuit is small, a high-speed operation type integrated circuit can be realized.

[Brief explanation of the drawing]

Fig. 1 is a plan view of a conventional integrated circuit, Fig. 2 is a plan view of an embodiment of the present invention, and Figs. It is a diagram. In the figure, 101, 304... one conductivity type silicon substrate, 102, 106, 31, 313, 314, 3
15... Opposite conductivity type region, 104, 201, 30
6,307...gate electrode, 105,308...
First layer wiring electrode, 107, 202... Gate electrode opening and exposed surface of gate electrode, 103, 3
21... Second layer aluminum wiring, 11
0,210...transistor, 120,220...
...Indicates a capacitive element.

Claims (1)

[Claims] 1 In a planar shape, a girder line extends in one direction, a word line extends in a direction perpendicular to the one direction, one of the source and drain regions of an insulated gate field effect transistor is connected to the girder line, and the transistor and a thick insulating film selectively provided on the semiconductor substrate, a capacitive element coupled to the transistor is provided, and the word line is connected to the gate electrode of the transistor and extends over the capacitive element in the perpendicular direction. In the existing semiconductor device, a thermal oxide film is deposited on the sides of the gate electrode, and the upper surface of the gate electrode above the operating area of the transistor is entirely in the perpendicular direction, which is the width direction of the gate electrode. The word line has an exposed surface that is exposed across the entire width of the upper surface of the gate electrode on the operating region through the exposed surface, and the word line A semiconductor device, characterized in that the semiconductor device extends from above in a direction perpendicular to the planar shape on the capacitive element.