JPS6232691U - - Google Patents
Info
- Publication number
- JPS6232691U JPS6232691U JP12344885U JP12344885U JPS6232691U JP S6232691 U JPS6232691 U JP S6232691U JP 12344885 U JP12344885 U JP 12344885U JP 12344885 U JP12344885 U JP 12344885U JP S6232691 U JPS6232691 U JP S6232691U
- Authority
- JP
- Japan
- Prior art keywords
- voltage source
- resistor
- memory
- zener diode
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
Description
第１図は本考案の実施例、第２図は従来のメモ
リ保護回路を使用したＣＡＴＶコンバータのブロ
ツク構成図、第３図は第２図のメモリ保護回路の
動作説明図、第４図は本考案の動作説明図である
。
１……入力端子、２……出力端子、３……ＲＦ
部、４……ＲＦ処理回路、５……デイスクランブ
ル回路、６……インターフエース、７……ＣＰＵ
、８……バツクアツプメモリ、９……電源部、１
０……−５Ｖ電源回路、１１……−２０Ｖ電源回
路、１２……電圧検出回路、１３……コンパレー
タ、１４……基準電圧源、１５……リセツト回路
、１６，１７……トランジスタ、１８，１９……
ツエナーダイオード、２０，２１，２２，２３…
…抵抗、２４……コンデンサ、２５……インバー
タ。
Fig. 1 is an embodiment of the present invention, Fig. 2 is a block diagram of a CATV converter using a conventional memory protection circuit, Fig. 3 is an explanatory diagram of the operation of the memory protection circuit shown in Fig. 2, and Fig. 4 is a diagram of the present invention. It is an explanatory diagram of the operation of the invention. 1...Input terminal, 2...Output terminal, 3...RF
part, 4...RF processing circuit, 5...descramble circuit, 6...interface, 7...CPU
, 8... Backup memory, 9... Power supply section, 1
0...-5V power supply circuit, 11...-20V power supply circuit, 12...Voltage detection circuit, 13...Comparator, 14...Reference voltage source, 15...Reset circuit, 16, 17...Transistor, 18, 19...
Zener diode, 20, 21, 22, 23...
...Resistor, 24...Capacitor, 25...Inverter.
Claims (1)
もにリセツト入力端子を有し該入力端子への入力
信号によつて前記内蔵メモリに記憶された記憶情
報を前記バツクアツプメモリへ転送するようにプ
ログラムされたＣＰＵと、前記ＣＰＵとバツクア
ツプメモリとに電源電圧を供給する第１の電圧源
と、前記第１の電圧源よりも高い電圧の第２の電
圧源と、該電圧源と前記ＣＰＵのリセツト入力端
子との間に接続されたリセツト回路からなるメモ
リ保護回路であつて、前記リセツト回路は前記第
２の電圧源の高電位端に一端が接続された第１の
抵抗と該抵抗の他端にそのカソードが接続される
とともにアノードが前記第２の電圧源の低電位端
に接続された第１のツエナーダイオードとからな
る第１の直列回路と、前記高電位端にカソードが
接続された第２のツエナーダイオードのアノード
と前記低電位端との間に接続された第２の抵抗と
からなる第２の直列回路と、前記第１の抵抗と第
１とのツエナーダイオードとの接続点にベースが
接続されるとともに前記第２の抵抗と第２のツエ
ナーダイオードとの接続点にエミツタが接続され
たトランジスタとから構成され、前記第１と第２
のツエナーダイオードのツエナー電圧を前記第２
の電圧源の印加状態で前記トランジスタのベース
とエミツタ電圧がほぼ等しくなる如く設定し、該
トランジスタのコレクタから前記ＣＰＵのリセツ
ト入力端子に信号を入力するようにしたことを特
徴とするメモリ保護回路。 a backup memory; a CPU having a built-in memory and having a reset input terminal and programmed to transfer stored information stored in the built-in memory to the backup memory by an input signal to the input terminal; , a first voltage source that supplies a power supply voltage to the CPU and the backup memory, a second voltage source having a higher voltage than the first voltage source, and a reset input terminal of the voltage source and the CPU. The memory protection circuit includes a first resistor having one end connected to the high potential end of the second voltage source, and a first resistor having its cathode connected to the other end of the resistor. and a first Zener diode having an anode connected to the low potential end of the second voltage source; and a second Zener diode having a cathode connected to the high potential end of the second voltage source. A second series circuit including a second resistor connected between the anode of the diode and the low potential end, and a base connected to a connection point between the first resistor and the first Zener diode. and a transistor whose emitter is connected to a connection point between the second resistor and the second Zener diode, and the first and second
The Zener voltage of the Zener diode is
A memory protection circuit characterized in that the base and emitter voltages of the transistor are set to be approximately equal when a voltage source is applied, and a signal is input from the collector of the transistor to the reset input terminal of the CPU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12344885U JPS6232691U (en) | 1985-08-10 | 1985-08-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12344885U JPS6232691U (en) | 1985-08-10 | 1985-08-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6232691U true JPS6232691U (en) | 1987-02-26 |
Family
ID=31014561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12344885U Pending JPS6232691U (en) | 1985-08-10 | 1985-08-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6232691U (en) |
-
1985
- 1985-08-10 JP JP12344885U patent/JPS6232691U/ja active Pending
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